LuminaSensum/arm-trusted-firmware

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LuminaSensum / arm-trusted-firmware

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2018-07-24	587f60f Browse files » stm32mp1: Add device tree files ... Those device tree files are taken from STM32MP1 U-Boot and Linux. And they are updated to fit TF-A needs. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Yann Gautier committed on 24 Jul 2018
	10a511c Browse files » stm32mp1: Add DDR support and its security with TZC400 ... The DDR driver is under dual license, BSD and GPLv2. The configuration parameters are taken from device tree. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Yann Gautier committed on 24 Jul 2018
	e4f559f Browse files » stm32mp1: Add PMIC support ... If a PMIC companion chip is present on board, it has to be configured for regulators supplies. This check is done with board DT configuration. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Pascal Paillet <p.paillet@st.com> Yann Gautier committed on 24 Jul 2018
	6a339a4 Browse files » stm32mp1: Add GPIO support ... The management of pinctrl nodes of device tree is also added. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Yann Gautier committed on 24 Jul 2018
	7839a05 Browse files » stm32mp1: Add clock and reset support ... The clock driver is under dual license, BSD and GPLv2. The clock driver uses device tree, so a minimal support for this is added. The required files for driver and DTS files are in include/dt-bindings/. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Yann Gautier committed on 24 Jul 2018
	4353bb2 Browse files » Introduce STMicroelectronics STM32MP1 platform ... STM32MP1 is a microprocessor designed by STMicroelectronics, based on a dual Arm Cortex-A7. It is an Armv7-A platform, using dedicated code from TF-A. STM32MP1 uses BL2 compiled with BL2_AT_EL3. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Pascal Paillet <p.paillet@st.com> Yann Gautier committed on 24 Jul 2018
	Unverified 790e6c5 Browse files » Merge pull request #1485 from jeenu-arm/ras ... Double-fault and fatal error handling support danh-arm authored on 24 Jul 2018 GitHub committed on 24 Jul 2018
2018-07-19	Unverified ba0248b Browse files » Merge pull request #1450 from MISL-EBU-System-SW/marvell-support-v6 ... Marvell support for Armada 8K SoC family danh-arm authored on 19 Jul 2018 GitHub committed on 19 Jul 2018
	Unverified 224e1ab Browse files » Merge pull request #1481 from antonio-nino-diaz-arm/an/xlat-refactor ... xlat: More refactoring danh-arm authored on 19 Jul 2018 GitHub committed on 19 Jul 2018
	Unverified 8ff0dfa Browse files » Merge pull request #1482 from sandrine-bailleux-arm/sb/fix-hcptr ... Misc arch.h fixes and cleanup danh-arm authored on 19 Jul 2018 GitHub committed on 19 Jul 2018
	b56dc2a Browse files » RAS: Introduce handler for Uncontainable errors ... Uncontainable errors are the most severe form of errors, which typically mean that the system state can't be trusted any more. This further means that normal error recovery process can't be followed, and an orderly shutdown of the system is often desirable. This patch allows for the platform to define a handler for Uncontainable errors received. Due to the nature of Uncontainable error, the handler is expected to initiate an orderly shutdown of the system, and therefore is not expected to return. A default implementation is added which falls back to platform unhandled exception. Also fix ras_arch.h header guards. Change-Id: I072e336a391a0b382e77e627eb9e40729d488b55 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> Jeenu Viswambharan committed on 19 Jul 2018
2018-07-18	486f868 Browse files » plat: marvell: Add common ARMADA platform components ... Add common Marvell ARMADA platform components. This patch also includes common components for Marvell ARMADA 8K platforms. Change-Id: I42192fdc6525a42e46b3ac2ad63c83db9bcbfeaf Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin committed on 18 Jul 2018
	f87e944 Browse files » marvell: drivers: Add i2c driver ... Add i2c driver for A8K SoC family. Change-Id: I5932b2fce286d84fc3ad5a74c4c456001faa3196 Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin committed on 18 Jul 2018
	d5a6f86 Browse files » marvell: drivers: Add thermal driver ... Add thermal driver for A8K SoC family. The termal unit data is used by Marvell DRAM initialization code for optimizing the memory controller configuration Change-Id: Iad92689fa6e4224a89d872e9aa015393abd9cf73 Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin committed on 18 Jul 2018
	152b0e4 Browse files » marvell: drivers: Add L3/system cache management drivers ... Add LLC (L3) cache management drivers for Marvell SoCs AP806, AP807 and AP810 Change-Id: Ic70710f9bc5b6b48395d62212df7011e2fbb5894 Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin committed on 18 Jul 2018
	bc6206f Browse files » lib: cpu: Add L2 cache aux control register definition to CA72 ... Add definition of EL1 L2 Auxilary Control register to Cortex A72 library headers. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin committed on 18 Jul 2018
	031542f Browse files » marvell: drivers: Add MoChi drivers ... Add ModularChip and MCI drivers for A8K SoC family. ModularChip drivers include support for the internal building blocks of Marvell ARMADA SoCs - APN806, APN807 and CP110 Change-Id: I9559343788fa2e5eb47e6384a4a7d47408787c02 Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin committed on 18 Jul 2018
	c0474d5 Browse files » marvell: drivers: Add address decoding units drivers ... Add address decoding unit drivers for Marvell SoCs. Address decoding flow and address translation units chart are located at docs/marvell/misc/mvebu-a8k-addr-map.txt Change-Id: Id6ce311fa1f4f112df3adfac5d20449f495f71ed Signed-off-by: Hanna Hawa <hannah@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin committed on 18 Jul 2018
	e62ea09 Browse files » Fix HCPTR.TCP11 bit definition ... Change-Id: I98f23f6cebcf984b57efc5449b75ff702e1984a0 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Sandrine Bailleux committed on 18 Jul 2018
	3039988 Browse files » Fix types of arch.h definitions ... Define the values as unsigned int or unsigned long long based on the actual size of the register. This prevents subtle issues caused by having a type that is too small. For example: #define OPTION_ENABLE 0x3 #define OPTION_SHIFT 32 uint64_t mask = OPTION_ENABLE << OPTION_SHIFT; Because OPTION_ENABLE fits in an int, the value is considered an int. This means that, after shifting it 32 places to the left, the final result is 0. The correct way to define the values is: #define OPTION_ENABLE ULL(0x3) #define OPTION_SHIFT U(32) In this case, the compiler is forced to use a 64 bit value from the start, so shifting it 32 places to the left results in the expected value. Change-Id: Ieaf2ffc2d8caa48c622db011f2aef549e713e019 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Antonio Nino Diaz committed on 18 Jul 2018
	0107aa4 Browse files » Add missing parentheses to macros in arch.h ... Change-Id: Ifea46da46d1bfd01b341acfad75df5bcab48a204 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Antonio Nino Diaz committed on 18 Jul 2018
	Unverified 344e403 Browse files » Merge pull request #1480 from sandrine-bailleux-arm/topics/sb/debug-macros ... Always compile debug macros Soby Mathew authored on 18 Jul 2018 GitHub committed on 18 Jul 2018
2018-07-15	1dd6c05 Browse files » xlat: Remove references to the Trusted Firmware ... This library can be used in other projects. All comments that talk about the Trusted Firmware should be talking about the library itself. Change-Id: I3b98d42f7132be72c1f8a4900acfaa78dbd2daa2 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Antonio Nino Diaz committed on 15 Jul 2018
2018-07-15	63ddbae Browse files » xlat v2: Make setup_mmu_config public ... This allows other parts of the code to reuse it. No functional changes. Change-Id: Ib052ae235c422d9179958bd3016c3e678779ae9b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Antonio Nino Diaz committed on 15 Jul 2018
2018-07-13	Unverified 9ceda8b Browse files » Merge pull request #1477 from dp-arm/dp/css-ap-core ... CSS: Add support for SCMI AP core config protocol Dimitris Papastamos authored on 13 Jul 2018 GitHub committed on 13 Jul 2018
	6563c0b Browse files » xlat v2: Turn MMU parameters into 64-bit values ... Most registers are 64-bit wide, even in AArch32 mode: - MAIR_ELx is equivalent to MAIR0 and MAIR1. - TTBR is 64 bit in both AArch64 and AArch32. The only difference is the TCR register, which is 32 bit in AArch32 and in EL3 in AArch64. For consistency with the rest of ELs in AArch64, it makes sense to also have it as a 64-bit value. Change-Id: I2274d66a28876702e7085df5f8aad0e7ec139da9 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Antonio Nino Diaz committed on 13 Jul 2018
	aa1d5f6 Browse files » xlat v2: Remove IMAGE_EL define ... The Exception Level is now detected at runtime. This means that it is not needed to hardcode the EL used by each image. This doesn't result in a substantial increase of the image size because the initialization functions that aren't used are garbage-collected by the linker. In AArch32 the current EL has been changed from EL3 to EL1 because the the AArch32 PL1&0 translation regime behaves more like the AArch64 EL1&0 translation regime than the EL3 one. Change-Id: I941404299ebe7666ca17619207c923b49a55cb73 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Antonio Nino Diaz committed on 13 Jul 2018
	cf24229 Browse files » Run compiler on debug macros for type checking ... Even if the log output is too low for a message to be printed out on the console by the debug macros, it should still be evaluated by the compiler to get some type checking and validation of the format specifiers. To do so, introduce the no_tf_log() macro that encloses the call to tf_log() in an always-false condition. This avoids the problem of discovering build issues only when we build the firmware with the right LOG_LEVEL value. Change-Id: Ic0fd252ab691d0187fd925756a4837aca1cbfd7b Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Sandrine Bailleux committed on 13 Jul 2018
2018-07-12	Unverified b19269a Browse files » Merge pull request #1432 from Yann-lms/mmc_framework ... [RFC] Add MMC framework Dimitris Papastamos authored on 12 Jul 2018 GitHub committed on 12 Jul 2018
2018-07-12	2a246d2 Browse files » CSS: Use SCMI AP core protocol to set the warm boot entrypoint ... Change-Id: Iaebbeac1a1d6fbd531e5694b95ed068b7a193e62 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Dimitris Papastamos committed on 12 Jul 2018