Fork: 0
LuminaSensum / arm-trusted-firmware
Browse code
lib: cpu: Add L2 cache aux control register definition to CA72
Add definition of EL1 L2 Auxilary Control register to
Cortex A72 library headers.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
WIP_v2.3-LS master v2.2-LS v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3 v2.2-rc2 v2.2-rc1 v2.2-rc0 v2.2 v2.1-rc1 v2.1-rc0 v2.1 v2.0-rc0 v2.0 v1.6-rc1 v1.6-rc0 v1.6
1 parent 031542f commit bc6206f7f62ec8e466bbab82dd576bc8489486e2
@Konstantin Porotchkin Konstantin Porotchkin authored on 5 Jul 2018
Patch
Unified Split
Showing 1 changed file
View
include/lib/cpus/aarch64/cortex_a72.h