plat: imx8mn: Add imx8mn basic support ...

Add imx8mn basic support

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ibdfcc87700bfaf980e429f3a5fa08515218ae78d

Merge "Tegra: enable SDEI handling" into integration

Merge "Tegra194: validate C6 power state type" into integration

Merge "Tegra194: remove support for CPU suspend power down state" into integration

Merge "FVP: Add support for passing platform's topology to DTS" into integration

Merge "plat/fvp: Support for extracting UART serial node info from DT" into integration

plat/fvp: Support for extracting UART serial node info from DT ...

This patch introduces the populate function which leverages
a new driver to extract base address and clk frequency properties
of the uart serial node from HW_CONFIG device tree.

This patch also introduces fdt helper API fdtw_translate_address()
which helps in performing address translation.

Change-Id: I053628065ebddbde0c9cb3aa93d838619f502ee3
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

Merge "Enable v8.6 WFE trap delays" into integration

Tegra: enable SDEI handling ...

This patch enables SDEI support for all Tegra platforms, with
the following configuration settings.

* SGI 8 as the source IRQ
* Special Private Event 0
* Three private, dynamic events
* Three shared, dynamic events
* Twelve general purpose explicit events

Verified using TFTF SDEI test suite.

******************************* Summary *******************************
 Test suite 'SDEI'                                               Passed
 =================================
 Tests Skipped : 0
 Tests Passed  : 5
 Tests Failed  : 0
 Tests Crashed : 0
 Total tests   : 5
 =================================

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I1922069931a7876a4594e53260ee09f2e4f09390

Merge "plat/fvp: Populate GICv3 parameters dynamically" into integration

Merge "Tegra: enable stack protection" into integration

Enable v8.6 WFE trap delays ...

This patch enables the v8.6 extension to add a delay before WFE traps
are taken. A weak hook plat_arm_set_twedel_scr_el3 has been added in
plat/common/aarch64/plat_common.c that disables this feature by default
but platform-specific code can override it when needed.

The only hook provided sets the TWED fields in SCR_EL3, there are similar
fields in HCR_EL2, SCTLR_EL2, and SCTLR_EL1 to control WFE trap delays in
lower ELs but these should be configured by code running at EL2 and/or EL1
depending on the platform configuration and is outside the scope of TF-A.

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I0a9bb814205efeab693a3d0a0623e62144abba2d

plat/fvp: Populate GICv3 parameters dynamically ...

Query the GICD and GICR base addresses in runtime using fconf getter
APIs.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I309fb2874f3329ddeb8677ddb53ed4c02199a1e9

Merge "Fix exception in save/restore of EL2 registers." into integration

Fix exception in save/restore of EL2 registers. ...

Removing FPEXC32_EL2 from the register save/restore routine for EL2
registers since it is already a part of save/restore routine for
fpregs.

Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: I5ed45fdbf7c8efa8dcfcd96586328d4f6b256bc4

FVP: Add support for passing platform's topology to DTS ...

This patch adds support for passing FVP platform's topology
configuration to DTS files for compilation, which allows to
build DTBs with correct number of clusters and CPUs.
This removes non-existing clusters/CPUs from the compiled
device tree blob and fixes reported Linux errors when trying
to power on absent CPUs/PEs.
If DTS file is passed using FVP_HW_CONFIG_DTS build option from
the platform's makefile, FVP_CLUSTER_COUNT, FVP_MAX_CPUS_PER_CLUSTER
and FVP_MAX_PE_PER_CPU parameters are used, otherwise CI script will
use the default values from the corresponding DTS file.

Change-Id: Idcb45dc6ad5e3eaea18573aff1a01c9344404ab3
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

Merge "Fix compilation error when ENABLE_PIE=1" into integration

Tegra: enable stack protection ...

This patch sets ENABLE_STACK_PROTECTOR=strong and implements
the platform support to generate a stack protection canary value.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ia8afe464b5645917b1c77d49305d19c7cd01866a

Fix compilation error when ENABLE_PIE=1 ...

This patch fixes compilation errors when ENABLE_PIE=1.

<snip>
bl31/aarch64/bl31_entrypoint.S: Assembler messages:
bl31/aarch64/bl31_entrypoint.S:61: Error: invalid operand (*UND* section) for `~'
bl31/aarch64/bl31_entrypoint.S:61: Error: invalid immediate
Makefile:1079: recipe for target 'build/tegra/t194/debug/bl31/bl31_entrypoint.o' failed
<snip>

Verified by setting 'ENABLE_PIE=1' for Tegra platform builds.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ifd184f89b86b4360fda86a6ce83fd8495f930bbc

Merge "plat/arm/fvp: Support performing SDEI platform setup in runtime" into integration

plat/arm/fvp: Support performing SDEI platform setup in runtime ...

This patch introduces dynamic configuration for SDEI setup and is supported
when the new build flag SDEI_IN_FCONF is enabled. Instead of using C arrays
and processing the configuration at compile time, the config is moved to
dts files. It will be retrieved at runtime during SDEI init, using the fconf
layer.

Change-Id: If5c35a7517ba00a9f258d7f3e7c8c20cee169a31
Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
Co-authored-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

Merge "Tegra: introduce support for SMCCC_ARCH_SOC_ID" into integration

Merge "Implement workaround for AT speculative behaviour" into integration

Implement workaround for AT speculative behaviour ...

During context switching from higher EL (EL2 or higher)
to lower EL can cause incorrect translation in TLB due to
speculative execution of AT instruction using out-of-context
translation regime.

Workaround is implemented as below during EL's (EL1 or EL2)
"context_restore" operation:
1. Disable page table walk using SCTLR.M and TCR.EPD0 & EPD1
   bits for EL1 or EL2 (stage1 and stage2 disabled)
2. Save all system registers except TCR and SCTLR (for EL1 and EL2)
3. Do memory barrier operation (isb) to ensure all
   system register writes are done.
4. Restore TCR and SCTLR registers (for EL1 and EL2)

Errata details are available for various CPUs as below:
Cortex-A76: 1165522
Cortex-A72: 1319367
Cortex-A57: 1319537
Cortex-A55: 1530923
Cortex-A53: 1530924

More details can be found in mail-chain:
https://lists.trustedfirmware.org/pipermail/tf-a/2020-April/000445.html

Currently, Workaround is implemented as build option which is default
disabled.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: If8545e61f782cb0c2dda7ffbaf50681c825bd2f0

Merge changes I35c5abd9,I99e64245 into integration ...

* changes:
  SPMD: extract SPMC DTB header size from SPMD
  SPMD: code/comments cleanup

Merge "doc: Reorganize maintainers.rst file" into integration

Merge "doc: Update various process documents" into integration

doc: Reorganize maintainers.rst file ...

The maintainers.rst file provides the list of all TF-A modules and their
code owners. As there are quite a lot of modules (and more to come) in
TF-A, it is sometimes hard to find the information.

Introduce categories (core code, drivers/libraries/framework, ...) and
classify each module in the right one.

Note that the core code category is pretty much empty right now but the
plan would be to expand it with further modules (e.g. PSCI, SDEI, TBBR,
...) in a future patch.

Change-Id: Id68a2dd79a8f6b68af5364bbf1c59b20c05f8fe7
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

doc: Update various process documents ...

Most of the changes consist in using the new code owners terminology
(from [1]).

[1] https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/

Change-Id: Icead20e9335af12aa47d3f1ac5d04ca157b20c82
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

SPMD: extract SPMC DTB header size from SPMD ...

Currently BL2 passes TOS_FW_CONFIG address and size through registers to
BL31. This corresponds to SPMC manifest load address and size. The SPMC
manifest is mapped in BL31 by dynamic mapping. This patch removes BL2
changes from generic code (which were enclosed by SPD=spmd) and retrieves
SPMC manifest size directly from within SPMD. The SPMC manifest load
address is still passed through a register by generic code.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I35c5abd95c616ae25677302f0b1d0c45c51c042f