LuminaSensum/arm-trusted-firmware

Fork: 0

LuminaSensum / arm-trusted-firmware

History for arm-trusted-firmware / plat

2019-06-28	5b6ebee Browse files » Remove MULTI_CONSOLE_API flag and references to it ... The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Ambroise Vincent committed on 28 Jun 2019
2019-06-19	fc3c382 Browse files » Merge changes from topic "yg/clk_syscfg_dt" into integration ... * changes: fdts: stm32mp1: realign device tree files with internal devs stm32mp1: increase device tree size to 20kB stm32mp1: make dt_get_stdout_node_offset() static stm32mp1: use unsigned values for SDMMC defines stm32mp1: remove useless LIBFDT_SRCS from PLAT_BL_COMMON_SOURCES stm32mp1: update doc for U-Boot compilation stm32mp1: add general SYSCFG management stm32mp1: move stm32_get_gpio_bank_clock() to private file clk: stm32mp1: correctly handle Clock Spreading Generator clk: stm32mp1: use defines for mask values in stm32mp1_clk_sel array clk: stm32mp1: move oscillator functions to generic file arch: add some defines for generic timer registers John Tsichritzis authored on 19 Jun 2019 TrustedFirmware Code Review committed on 19 Jun 2019
2019-06-17	de3ad4f Browse files » Merge changes If61ab215,I3e8b0251,I1757eee9,I81b48475,I46b445a7, ... into integration ... * changes: rcar_gen3: drivers: qos: Move QoS drivers out of staging rcar_gen3: drivers: qos: V3M: Configure DBSC QoS from a table rcar_gen3: drivers: qos: E3: Configure DBSC QoS from a table rcar_gen3: drivers: qos: D3: Configure DBSC QoS from a table rcar_gen3: drivers: qos: M3N: Configure DBSC QoS from a table rcar_gen3: drivers: qos: M3W: Configure DBSC QoS from a table rcar_gen3: drivers: qos: H3: Configure DBSC QoS from a table rcar_gen3: drivers: qos: Add function to configure DBSC QoS settings from a table rcar_gen3: drivers: qos: Fix checkpatch issues rcar_gen3: drivers: qos: V3M: Drop useless comments rcar_gen3: drivers: qos: V3M: Convert mstat table to uint64_t rcar_gen3: drivers: qos: V3M: Factor out mstat fix into separate file rcar_gen3: drivers: qos: V3M: Use common register definition rcar_gen3: drivers: qos: E3: Drop extra level of nesting rcar_gen3: drivers: qos: E3: Use common register definition rcar_gen3: drivers: qos: D3: Replace ad-hoc register addresses with macros rcar_gen3: drivers: qos: D3: Drop MD pin check rcar_gen3: drivers: qos: D3: Make DBSC settings local to dbsc_setting() rcar_gen3: drivers: qos: D3: Drop useless comments rcar_gen3: drivers: qos: D3: Convert mstat table to uint64_t rcar_gen3: drivers: qos: D3: Factor out mstat fix into separate file rcar_gen3: drivers: qos: D3: Use common register definition rcar_gen3: drivers: qos: M3N: Fix checkpatch issues rcar_gen3: drivers: qos: M3N: Drop MD pin check rcar_gen3: drivers: qos: M3N: Drop useless comments rcar_gen3: drivers: qos: M3N: Drop extra level of nesting rcar_gen3: drivers: qos: M3N: Use common register definition rcar_gen3: drivers: qos: M3W: Fix checkpatch issues rcar_gen3: drivers: qos: M3W: Drop MD pin check rcar_gen3: drivers: qos: M3W: Drop useless comments rcar_gen3: drivers: qos: M3W: Drop extra level of nesting rcar_gen3: drivers: qos: M3W: Convert mstat table to uint64_t rcar_gen3: drivers: qos: M3W: Factor out mstat fix into separate file rcar_gen3: drivers: qos: M3W: Use common register definition rcar_gen3: drivers: qos: H3: Fix checkpatch issues rcar_gen3: drivers: qos: H3: Drop MD pin check rcar_gen3: drivers: qos: H3: Drop useless comments rcar_gen3: drivers: qos: H3: Drop extra level of nesting rcar_gen3: drivers: qos: H3: Convert mstat table to uint64_t rcar_gen3: drivers: qos: H3: Factor out mstat fix into separate file rcar_gen3: drivers: qos: H3: Use common register definition rcar_gen3: console: Convert to multi-console API John Tsichritzis authored on 17 Jun 2019 TrustedFirmware Code Review committed on 17 Jun 2019
	c67703e Browse files » rcar_gen3: drivers: qos: Move QoS drivers out of staging ... Now that QoS drivers are cleaned up , move them out of staging. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: If61ab2157c30b8f5a6b91d2c56ddbb9098ef99e8 Marek Vasut committed on 17 Jun 2019
	0a01677 Browse files » stm32mp1: increase device tree size to 20kB ... Change-Id: Idee966b6434aa038e54b6e7176749a7b65bdbe84 Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier committed on 17 Jun 2019
	f805594 Browse files » stm32mp1: make dt_get_stdout_node_offset() static ... Do not export function dt_get_stdout_node_offset() that is used only inside stm32mp_dt.c source file. Change-Id: I9dd3dbfab21d42ed81c68723e71fe5a7586dce93 Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier committed on 17 Jun 2019
	29a5072 Browse files » stm32mp1: use unsigned values for SDMMC defines ... Correct SDMMC macros to define unsigned values as expected by the driver implementation. Change-Id: Ib009f3df2cf26a9759d129eb571a27b2564770ce Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier committed on 17 Jun 2019
	d304158 Browse files » stm32mp1: remove useless LIBFDT_SRCS from PLAT_BL_COMMON_SOURCES ... Remove inclusion of libfdt source files in source file list since these are already included from generic libfdt.mk makefile. Change-Id: If42624557c4d88ca85d70f83b1b08c58f50afe72 Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier committed on 17 Jun 2019
	f33b243 Browse files » stm32mp1: add general SYSCFG management ... The system configuration controller is mainly used to manage the compensation cell and other IOs and system related settings. The SYSCFG driver is in charge of configuring masters on the interconnect, IO compensation, low voltage boards, or pull-ups for boot pins. All other configurations should be handled in Linux drivers requiring it. Device tree files are also updated to manage vdd-supply regulator. Change-Id: I10fb513761a7d1f2b7afedca9c723ad9d1bccf42 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier committed on 17 Jun 2019
	8f282da Browse files » stm32mp1: move stm32_get_gpio_bank_clock() to private file ... GPIOx clocks are specific to each STM32MP platforms. This change moves function stm32_get_gpio_bank_clock() from stm32mp common source files to platform private stm32mp1_private.c source file. Change-Id: I9616c0d3fe4d10af715d6f2d1550c13ab62c829a Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier committed on 17 Jun 2019
	f66358a Browse files » clk: stm32mp1: move oscillator functions to generic file ... Those functions are generic for parsing nodes from device tree hence could be located in generic source file. The oscillators description structure is also moved to STM32MP1 clock driver, as it is no more used in stm32mp1_clkfunc and cannot be in a generic file. Change-Id: I93ba74f4eea916440fef9b160d306af1b39f17c6 Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier committed on 17 Jun 2019
	6acb509 Browse files » Merge "allwinner: Disable unused features to save space" into integration John Tsichritzis authored on 17 Jun 2019 TrustedFirmware Code Review committed on 17 Jun 2019
2019-06-13	018358f Browse files » rcar_gen3: console: Convert to multi-console API ... Convert the R-Car Gen3 platform and both SCIF and Log drivers to multi-console API. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I18556973937d150b60453f9150d54ee612571e35 Marek Vasut committed on 13 Jun 2019
2019-06-11	dd5deab Browse files » plat/arm: Skip BL2U if RESET_TO_SP_MIN flag is set ... BL2U should not build when RESET_TO_SP_MIN flag is set, like BL1 and BL2. Change-Id: Iac516121f98611ca1f58d2b5efdec6525b06ce4e Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> Louis Mayencourt committed on 11 Jun 2019
2019-06-10	cb60e71 Browse files » Merge changes from topic "jts/ti_fix" into integration ... * changes: ti: k3: common: Remove coherency workaround for AM65x ti: k3: common: Use coherent memory for shared data Soby Mathew authored on 10 Jun 2019 TrustedFirmware Code Review committed on 10 Jun 2019
2019-06-08	8f31853 Browse files » allwinner: Disable unused features to save space ... As all Allwinner platforms are single-cluster A53 chips, we can disable support for newer, unsupported architecture extensions. We can also avoid some cache maintenance code, since no platform-specific setup is required to enable coherency. These changes reduce the size of .text on a default build with GCC 9.1 enough that .vectors again fits in the second half of a page, instead of requiring its own page. This commit was boot-tested on the Pinebook. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Ib90454ef0c798d5e714b7780c585be0b1ed49c6d Samuel Holland committed on 8 Jun 2019
2019-06-06	74eaf26 Browse files » Merge "FVP: Remove GIC initialisation from secondary core cold boot" into integration John Tsichritzis authored on 6 Jun 2019 TrustedFirmware Code Review committed on 6 Jun 2019
	48d6b26 Browse files » ti: k3: common: Remove coherency workaround for AM65x ... We previously left our caches on during power-down to prevent any non-caching accesses to memory that is cached by other cores. Now with the last accessed areas all being marked as non-cached by USE_COHERENT_MEM we can rely on that to workaround our interconnect issues. Remove the old workaround. Change-Id: Idadb7696d1449499d1edff4f6f62ab3b99d1efb7 Signed-off-by: Andrew F. Davis <afd@ti.com> Andrew F. Davis authored on 25 Apr 2019 John Tsichritzis committed on 6 Jun 2019
	65f7b81 Browse files » ti: k3: common: Use coherent memory for shared data ... HW_ASSISTED_COHERENCY implies something stronger than just hardware coherent interconnect, specifically a DynamIQ capable ARM core. For K3, lets use WARMBOOT_ENABLE_DCACHE_EARLY to enable caches early and then let the caches get shut off on powerdown, to prevent data corruption we also need to USE_COHERENT_MEM so that any accesses to shared memory after this point is only to memory that is set as non-cached for all cores. Change-Id: Ib9337f012df0e0388237942607c501b6f3e2a949 Signed-off-by: Andrew F. Davis <afd@ti.com> Andrew F. Davis authored on 25 Apr 2019 John Tsichritzis committed on 6 Jun 2019
	16b49f6 Browse files » mediatek: mt8183: add mcsi driver ... add mcsi driver to support cache coherence. Change-Id: I94f5922783e5dbc6b7e92aa06464bc1f0177f00a Signed-off-by: kenny liang <kenny.liang@mediatek.com> kenny liang authored on 2 May 2019 John Tsichritzis committed on 6 Jun 2019
	28a773e Browse files » mediatek: mt8183: add GIC driver ... Add Mediatek GIC driver to support interrupt functions. Signed-off-by: kenny liang <kenny.liang@mediatek.com> Change-Id: I967a18f2e45b7bbc88c506dd4f1f40a745227ad9 kenny liang authored on 2 May 2019 John Tsichritzis committed on 6 Jun 2019
2019-06-05	9c29e5f Browse files » FVP: Remove GIC initialisation from secondary core cold boot ... During the secondary cores' cold boot path, the cores initialise the GIC CPU interface. However this is a redundant action since 1) the cores are powered down immediately after that, 2) the GIC CPU interface is initialised from scratch when the secondary cores are powered up again later. Moreover, this part of code was introducing a bug. In a GICv3 system, the GIC's CPU interface system registers must not be written without the core being marked as "awake" in the redistributor. However, this sequence was performing such accesses and this would cause those cores to hang. The hang was caused by the DSB instruction that would never complete because of the GIC not recognising those writes. For the two aforementioned reasons, the entire part of the GIC CPU interface initialisation is removed. Change-Id: I6c33a1edda69dd5b6add16a27390a70731b5532a Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> John Tsichritzis committed on 5 Jun 2019
2019-06-04	629d04f Browse files » Apply compile-time check for AArch64-only cores ... Some cores support only AArch64 mode. In those cores, only a limited subset of the AArch32 system registers are implemented. Hence, if TF-A is supposed to run on AArch64-only cores, it must be compiled with CTX_INCLUDE_AARCH32_REGS=0. Currently, the default settings for compiling TF-A are with the AArch32 system registers included. So, if we compile TF-A the default way and attempt to run it on an AArch64-only core, we only get a runtime panic. Now a compile-time check has been added to ensure that this flag has the appropriate value when AArch64-only cores are included in the build. Change-Id: I298ec550037fafc9347baafb056926d149197d4c Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> John Tsichritzis committed on 4 Jun 2019
2019-05-30	e9eed3f Browse files » Merge "rockchip: drop rockchip-specific imported linker symbols for bl31" into integration Paul Beesley authored on 30 May 2019 TrustedFirmware Code Review committed on 30 May 2019
2019-05-29	3e6945e Browse files » rockchip: drop rockchip-specific imported linker symbols for bl31 ... In the rockchip bl31 setup the __RO_START__ and __RO_END__ symbols are currently imported into special BL31_RO_* constants while the general code also imports them as BL_CODE_BASE and BL_CODE_END. So we can just use the general symbols and can drop the duplication. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: Ibf1b48ad80bed897247a1690a32711030479262d Heiko Stuebner committed on 29 May 2019
2019-05-28	4d384eb Browse files » Merge "plat: imx8m: Add the aipstz init to config peripheral access" into integration Soby Mathew authored on 28 May 2019 TrustedFirmware Code Review committed on 28 May 2019
2019-05-28	68b8ab0 Browse files » Merge changes from topic "for-upstream" into integration ... * changes: ti: k3: common: Set L2 latency on A72 cores ti: k3: common: Add support for J721E Soby Mathew authored on 28 May 2019 TrustedFirmware Code Review committed on 28 May 2019
2019-05-23	570948d Browse files » Merge "plat/meson/gxl: BL31: remove BL2 dependency" into integration Sandrine Bailleux authored on 23 May 2019 TrustedFirmware Code Review committed on 23 May 2019
2019-05-22	16a755f Browse files » ti: k3: common: Set L2 latency on A72 cores ... The Cortex-A72 based cores on K3 platforms can be clocked fast enough that an extra latency cycle is needed to ensure correct L2 access. Set the latency here for all A72 cores. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: Id534316dec1c1f326908efbfd964f219cda7386a Andrew F. Davis committed on 22 May 2019
2019-05-22	7c088e7 Browse files » ti: k3: common: Add support for J721E ... Enable Cortex-A72 support for J721E. Change-Id: I5bea5fb6ec45d1a9f8f2192d42da2cc03ae0f7ec Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Nishanth Menon authored on 22 Jun 2018 Andrew F. Davis committed on 22 May 2019