rcar_gen3: drivers: ddr-a: Synchronize tables ...

Synchronize the R-Car DDR-A driver, used on R-Car E3,
with Renesas ATF release 2.0.0 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: drivers: cpld: Move rcar_cpld_reset_cpu() into header ...

Move the rcar_cpld_reset_cpu() function into header file and zap the externs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: drivers: swdt: Access SCR in EL3 ...

The code runs in EL3, use EL3 accessors to manipulate the interrupt bit.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: drivers: auth-mod: Access SCTLR in EL3 ...

The code runs in EL3, use EL3 accessors to manipulate the cache bits.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: plat: Dump EL3 interrupt error registers ...

Since the interrupts are handled in EL3, dump the EL3 error registers
in case an error happens.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: plat: Enable programmable CPU reset address ...

The reset address is programmable on the R-Car Gen3, enable it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: plat: Disable IPMMU PV0 cache on E3 ...

Disable the IPMMU PV0 cache on E3 rev. 1.x .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: plat: Add E3 rev. 1.1 support ...

Add support for R-Car E3 silicon rev. 1.1

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: plat: Add missing platform auto-detection name ...

Add missing TARGET_NAME for the case where RCAR_LSI is set to AUTO,
which is platform auto-detection.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: plat: Clean up rcar_pwrc_code_copy_to_system_ram() ...

Call the function only from architecture setup and at the end of
suspend cycle instead of calling it all over the place.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: plat: Fix BL2 size check ...

Rename BL2_LIMIT to BL2_IMAGE_LIMIT and BL2_SYSRAM_LIMIT to BL2_LIMIT to
correctly set BL2_LIMIT value. Set correct DEVICE_SRAM_BASE to match the
hardware. Use BL2_END in rcar_configure_mmu_el3() to mark the cacheable
BL2 area.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: plat: Staticize memory maps ...

Staticize the platform memory map tables as they are only used within
the platform_common.c file.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: plat: Function cleanup ...

Replace foo_t with struct foo.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: plat: Fix cache line size ...

The CPU has cache line size of 64 Bytes, fix the cache line size.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: plat: Disable SVE ...

Apply 3872fc2d1fc5 ("Do not enable SVE on pre-v8.2 platforms") to
R-Car Gen3 too.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: plat: Add missing dependency to rcar_srecord ...

Add missing dependency on the bl2.elf and bl31.elf into the rcar_srecord
target, which uses those ELF files to generate the SRECs.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: plat: Rename H3 label ...

Rename the H3 label to avoid confusing clang, which generates an error
if the label is just H3. Rename it to RCARH3.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

rcar_gen3: plat: Drop ddr_regdef_len() ...

This function is unused and triggers clang error, drop it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

Merge pull request #1739 from Yann-lms/includes ...

stm32mp1: do not include platform header files directly in drivers

Merge pull request #1736 from antonio-nino-diaz-arm/an/maintainers ...

maintainers: Fix path of Marvell documentation

Merge pull request #1732 from jollysxilinx/integration ...

plat: xilinx: Clock and PLL EEMI API Support

Merge pull request #1737 from antonio-nino-diaz-arm/an/asm-assert ...

Remove ASM_ASSERTION check in Makefile

Merge pull request #1735 from antonio-nino-diaz-arm/an/load-image-v2 ...

plat/arm: Remove comment that mentions LOAD_IMAGE_V2

stm32mp1: do not include platform header files directly in drivers ...

Instead, only platform_def.h is included.
The required files to be included are added in stm32mp1_def.h.

Signed-off-by: Yann Gautier <yann.gautier@st.com>

zynqmp: pm: Invalidate unused APLL_TO_LPD clock ...

This clock does not drive any clock in LPD so there is no need for
Linux to try to initialize it.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

zynqmp: pm: Invalidate several clocks that Linux doesn't need to control ...

Linux has no reason to use these system and debug clocks and therefore
shouldn't access them. These clocks are marked as invalid in order to
prevent Linux from registering and querying them.

Note that despite clocks being marked as invalid a security issue
still remains in place as there is nothing that prevents the
non-secure world from gating these clocks and that way causing
damage to the system.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

zynqmp: pm: Add ACPU_FULL and ACPU_HALF clocks in the invalid list ...

These clocks are marked as invalid in order to prevent Linux from
registering them.

Note that despite clocks being marked as invalid a security issue
still remains in place as there is nothing that prevents the
non-secure world from gating these clocks and that way halt
the whole APU subsystem.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

zynqmp: pm: Fix model of ACPU clocks ...

In the existing model for ACPU clock the mux, divider, and gate were
represented as one clock and ACPU_HALF was modelled as child of
ACPU clock. This is not correct. ACPU clock model contains only
mux and the divider, and it has 2 children: ACPU_FULL and ACPU_HALF
clocks which have only gates. The models of ACPU and ACPU_HALF clocks
are fixed and ACPU_FULL clock is added.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

zynqmp: pm: Reimplement clock get parent EEMI API ...

Clock get parent EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll control registers.
Since linux still uses clock set parent API to get pre_src, post_src, div2
and bypasss, in the implementation of pm_clock_get_parent() we need to
workaround this by distinguishing two cases:
1) if the given clock ID corresponds to a PLL-related clock ID (*_PRE_SRC,
   *_POST_SRC, *_INT_MUX or *_PLL clock IDs); or
2) given clock ID is truly an on-chip clock.
For case 1) we'll map the call onto PLL-specific EEMI API with the
respective parameter ID. For case 2) the call is passed to the PMU.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

zynqmp: pm: Reimplement clock set parent EEMI API ...

Clock set parent EEMI API is reimplemented to use system-level clock
and pll EEMI APIs rather than direct MMIO read/write accesses to clock
and pll control registers.
Since linux still uses clock set parent API to set pre_src, post_src, div2
and bypass, in the implementation of pm_clock_set_parent() we need to
workaround this by distinguishing two cases:
1) if the given clock ID corresponds to a PLL-related clock ID (*_PRE_SRC,
*_POST_SRC, *_INT_MUX or *PLL clock IDs); or 2) given clock ID is truly
an on-chip clock.
For case 1) we'll map the call onto PLL set parameter EEMI API with the
respective parameter ID. Since clock set parent interface to EL1/2 receives
parent index (mux select value), the value is just passed to PMU.
Functions that appear to be unused after this change is made are removed.

Setting the parent of *PLL clocks, that actually model bypass, is not
possible. This is already ensured by the existing clock model having the
CLK_SET_RATE_NO_REPARENT flag. The API also doesn't allow changing the
bypass parent. Bypass is controlled only by the PMU firmware.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>