2016-09-12 |
GICv3: Allow either G1S or G0 interrupts to be configured
...
Currently the GICv3 driver mandates that platform populate
both G1S and G0 interrupts. However, it is possible that a
given platform is not interested in both the groups and
just needs to specify either one of them.
This patch modifies the `gicv3_rdistif_init()` & `gicv3_distif_init()`
functions to allow either G1S or G0 interrupts to be configured.
Fixes ARM-software/tf-issues#400
Change-Id: I43572b0e08ae30bed5af9334f25d35bf439b0d2b
Yatharth Kochar
committed
on 12 Sep 2016
|
2016-08-18 |
Merge pull request #678 from soby-mathew/sm/PSCI_AArch32
...
Introduce AArch32 support for PSCI library
danh-arm
authored
on 18 Aug 2016
GitHub
committed
on 18 Aug 2016
|
2016-08-17 |
Merge pull request #682 from sudeep-holla/gicv3_ns_intr
...
gicv3: disable Group1 NonSecure interrupts during core powerdown
danh-arm
authored
on 17 Aug 2016
GitHub
committed
on 17 Aug 2016
|
Merge pull request #680 from hzhuang1/emmc_cmd23_v2
...
emmc: support CMD23
danh-arm
authored
on 17 Aug 2016
GitHub
committed
on 17 Aug 2016
|
2016-08-11 |
emmc: support CMD23
...
Support CMD23. When CMD23 is used, CMD12 could be avoided.
Two scenarios:
1. CMD17 for single block, CMD18 + CMD12 for multiple blocks.
2. CMD23 + CMD18 for both single block and multiple blocks.
The emmc_init() should initialize whether CMD23 is supported
or not.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang
committed
on 11 Aug 2016
|
gicv3: disable Group1 NonSecure interrupts during core powerdown
...
As per the GICv3 specification, to power down a processor using GICv3
and allow automatic power-on if an interrupt must be sent to a processor,
software must set Enable to zero for all interrupt groups(by writing to
GICC_CTLR or ICC_IGRPEN{0,1}_EL1/3 as appropriate.
Also, NonSecure EL1 software may not be aware of the CPU power state
details and fail to choose right states that require quiescing the CPU
interface. So it's preferred that the PSCI implementation handles it as
it is fully aware of the CPU power states.
This patch adds disabling of Group1 NonSecure interrupts during processor
power down along with Group0 and Group1 Secure interrupts so that all the
interrupt groups are handled at once as per specification.
Change-Id: Ib564d773c9c4c41f2ca9471451c030e3de75e641
Sudeep Holla
committed
on 11 Aug 2016
|
2016-08-10 |
AArch32: Add console driver
...
This patch adds console drivers including the pl011 driver
for the AArch32 mode.
Change-Id: Ifd22520d370fca3e73dbbf6f2d97d6aee65b67dd
Soby Mathew
committed
on 10 Aug 2016
|
AArch32: Enable GIC and TZC support
...
This patch modifies GICv3 and TZC drivers to add AArch32 support.
No modifications are required for the GICv2 driver for AArch32 support.
The TZC driver assumes that the secure world is running in Little-Endian
mode to do 64 bit manipulations. Assertions are present to validate the
assumption.
Note: The legacy GICv3 driver is not supported for AArch32.
Change-Id: Id1bc75a9f5dafb9715c9500ca77b4606eb1e2458
Soby Mathew
committed
on 10 Aug 2016
|
2016-08-09 |
Move console drivers to AArch64 folder
...
This patch moves the various assembly console drivers
into `aarch64` architecture specific folder. Stub files,
which include files from new location, are retained at the
original location for platform compatibility reasons.
Change-Id: I0069b6c1c0489ca47f5204d4e26e3bc3def533a8
Soby Mathew
committed
on 9 Aug 2016
|
2016-08-03 |
io: block: fix unaligned buffer
...
If buffer address parameter isn't aligned, it may cause
DMA issue in block device driver, as eMMC. Now check the buffer
address. If it's not aligned, use temporary buffer in io block
driver instead.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang
committed
on 3 Aug 2016
|
2016-07-27 |
GICv3: Fix the GICD_IROUTER offset
...
This patch fixes the offset of GICD_IROUTER register defined in gicv3.h.
Although the GICv3 documention mentions that the offset for this register
is 0x6100-0x7FD8, the offset calculation for an interrupt id `n` is :
0x6000 + 8n, where n >= 32
This requires the offset for GICD_IROUTER to be defined as 0x6000.
Fixes ARM-software/tf-issues#410
Change-Id: If9e91e30d946afe7f1f60fea4f065c7567093fa8
Soby Mathew
committed
on 27 Jul 2016
|
2016-07-18 |
Rework type usage in Trusted Firmware
...
This patch reworks type usage in generic code, drivers and ARM platform files
to make it more portable. The major changes done with respect to
type usage are as listed below:
* Use uintptr_t for storing address instead of uint64_t or unsigned long.
* Review usage of unsigned long as it can no longer be assumed to be 64 bit.
* Use u_register_t for register values whose width varies depending on
whether AArch64 or AArch32.
* Use generic C types where-ever possible.
In addition to the above changes, this patch also modifies format specifiers
in print invocations so that they are AArch64/AArch32 agnostic. Only files
related to upcoming feature development have been reworked.
Change-Id: I9f8c78347c5a52ba7027ff389791f1dad63ee5f8
Soby Mathew
committed
on 18 Jul 2016
|
2016-07-07 |
GIC: Ensure SGIs and PPIs are Group0 before setup
...
The legacy GIC driver assumes that the SGIs and PPIs are Group0 during
initialization. This is true if the driver is the first one to initialize
the GIC hardware after reset. But in some cases, earlier BL stages could
have already initialized the GIC hardware which means that SGI and PPI
configuration are not the expected reset values causing assertion failure
in `gicd_set_ipriorityr()`. This patch explicitly resets the SGI and PPI
to Group0 prior to their initialization in the driver. The same patch is
not done in the GICv2-only driver because unlike in the legacy driver,
`gicd_set_ipriorityr()` of GICv2 driver doesn't enforce this policy and
the appropriate group is set irrespective of the initial value.
Fixes ARM-software/tf-issues#396
Change-Id: I521d35caa37470ce542c796c2ba99716e4763105
Soby Mathew
committed
on 7 Jul 2016
|
2016-06-13 |
Merge pull request #629 from ljerry/tf_issue_398
...
Bring IO storage dummy driver
danh-arm
authored
on 13 Jun 2016
GitHub
committed
on 13 Jun 2016
|
2016-06-03 |
Allow dynamic overriding of ROTPK verification
...
A production ROM with TBB enabled must have the ability to boot test software
before a real ROTPK is deployed (e.g. manufacturing mode). Previously the
function plat_get_rotpk_info() must return a valid ROTPK for TBB to succeed.
This patch adds an additional bit `ROTPK_NOT_DEPLOYED` in the output `flags`
parameter from plat_get_rotpk_info(). If this bit is set, then the ROTPK
in certificate is used without verifying against the platform value.
Fixes ARM-software/tf-issues#381
Change-Id: Icbbffab6bff8ed76b72431ee21337f550d8fdbbb
Soby Mathew
committed
on 3 Jun 2016
|
2016-05-27 |
Merge pull request #632 from rockchip-linux/support-for-gpio-driver-v2
...
rockchip/rk3399: Support the gpio driver and configure
danh-arm
committed
on 27 May 2016
|
2016-05-26 |
gpio: support gpio set/get pull status
...
On some platform gpio can set/get pull status when input, add these
function so we can set/get gpio pull status when need it. And they are
optional function.
Caesar Wang
committed
on 26 May 2016
|
2016-05-25 |
CCN: Add API to query the PART0 ID from CCN
...
This patch adds the API `ccn_get_part0_id` to query the PART0 ID from the
PERIPHERAL_ID 0 register in the CCN driver. This ID allows to distinguish
the variant of CCN present on the system and possibly enable dynamic
configuration of the IP based on the variant. Also added an assert in
`ccn_master_to_rn_id_map()` to ensure that the master map bitfield provided
by the platform is within the expected interface id.
Change-Id: I92d2db7bd93a9be8a7fbe72a522cbcba0aba2d0e
Soby Mathew
committed
on 25 May 2016
|
2016-05-20 |
Implement generic delay timer
...
Add delay timer implementation based on the system generic counter.
This either uses the platform's implementation of
`plat_get_syscnt_freq()` or explicit clock multiplier/divider values
provided by the platform.
The current implementation of udelay has been modified to avoid
unnecessary calculations while waiting on the loop and to make it
easier to check for overflows.
Change-Id: I9062e1d506dc2f68367fd9289250b93444721732
Antonio Nino Diaz
committed
on 20 May 2016
|
2016-05-12 |
Bring IO storage dummy driver
...
Allow to handle cases where some images are pre-loaded (by debugger for
instance) without introducing many switches in files calling load_* functions.
Fixes: arm-software/tf-issues#398
Signed-off-by: Gerald Lejeune <gerald.lejeune@st.com>
Gerald Lejeune
committed
on 12 May 2016
|
2016-04-27 |
drivers: add emmc stack
...
In a lot of embedded platforms, eMMC device is the only one storage
device. So loading content from eMMC device is required in ATF.
Create the emmc stack that could co-work with IO block driver.
Support to read/write/erase eMMC blocks on both rpmb and normal
user area. Support to change the IO speed and bus width.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang
committed
on 27 Apr 2016
|
IO: support block device type
...
FIP is accessed as memory-mapped type. eMMC is block device type.
In order to support FIP based on eMMC, add the new io_block layer.
io_block always access eMMC device as block size. And it'll only
copy the required data into buffer in io_block driver. So preparing
an temporary buffer is required.
When use io_block device, MAX_IO_BLOCK_DEVICES should be declared
in platform_def.h. It's used to support multiple block devices.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang
committed
on 27 Apr 2016
|
2016-04-12 |
Use unsigned long long instead of uintptr_t in TZC400/DMC500 drivers
...
Currently the `tzc400_configure_region` and `tzc_dmc500_configure_region`
functions uses uintptr_t as the data type for `region_top` and `region_base`
variables, which will be converted to 32/64 bits for AArch32/AArch64
respectively. But the expectation is to keep these addresses at least 64 bit.
This patch modifies the data types to make it at least 64 bit by using
unsigned long long instead of uintptr_t for the `region_top` and
`region_base` variables. It also modifies the associated macros
`_tzc##fn_name##_write_region_xxx` accordingly.
Change-Id: I4e3c6a8a39ad04205cf0f3bda336c3970b15a28b
Yatharth Kochar
committed
on 12 Apr 2016
|
2016-04-08 |
Merge pull request #569 from Xilinx/zynqmp-v1
...
Support for Xilinx Zynq UltraScale+ MPSoC
danh-arm
committed
on 8 Apr 2016
|
2016-04-07 |
Merge pull request #575 from soby-mathew/sm/new_tzc_driver
...
Refactor the TZC driver and add DMC-500 driver
danh-arm
committed
on 7 Apr 2016
|
2016-04-01 |
drivers: Add Cadence UART driver
...
Add a driver for the Cadence UART which is found in Xilinx Zynq SOCs.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Soren Brinkmann
committed
on 1 Apr 2016
|
2016-03-31 |
Add ARM CoreLink DMC-500 driver to program TrustZone protection
...
The ARM CoreLink DMC-500 Dynamic Memory Controller provides the
programmable address region control of a TrustZone Address Space
Controller. The access permissions can be defined for eight
separate address regions plus a background or default region.
This patch adds a DMC-500 driver to define address regions and
program their access permissions as per ARM 100131_0000_02_en
(r0p0) document.
Change-Id: I9d33120f9480d742bcf7937e4b876f9d40c727e6
Vikram Kanigiri
authored
on 29 Jan 2016
Soby Mathew
committed
on 31 Mar 2016
|
Refactor the ARM CoreLink TZC-400 driver
...
TrustZone protection can be programmed by both memory and TrustZone
address space controllers like DMC-500 and TZC-400. These peripherals
share a similar programmer's view.
Furthermore, it is possible to have multiple instances of each type of
peripheral in a system resulting in multiple programmer's views.
For example, on the TZC-400 each of the 4 filter units can be enabled
or disabled for each region. There is a single set of registers to
program the region attributes. On the DMC-500, each filter unit has its
own programmer's view resulting in multiple sets of registers to program
the region attributes. The layout of the registers is almost the same
across all these variations.
Hence the existing driver in `tzc400\tzc400.c` is refactored into the
new driver in `tzc\tzc400.c`. The previous driver file is still maintained
for compatibility and it is now deprecated.
Change-Id: Ieabd0528e244582875bc7e65029a00517671216d
Vikram Kanigiri
authored
on 28 Jan 2016
Soby Mathew
committed
on 31 Mar 2016
|
TBB: add non-volatile counter support
...
This patch adds support for non-volatile counter authentication to
the Authentication Module. This method consists of matching the
counter values provided in the certificates with the ones stored
in the platform. If the value from the certificate is lower than
the platform, the boot process is aborted. This mechanism protects
the system against rollback.
The TBBR CoT has been updated to include this method as part of the
authentication process. Two counters are used: one for the trusted
world images and another for the non trusted world images.
** NEW PLATFORM APIs (mandatory when TBB is enabled) **
int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr);
This API returns the non-volatile counter value stored
in the platform. The cookie in the first argument may be
used to select the counter in case the platform provides
more than one (i.e. TBSA compliant platforms must provide
trusted and non-trusted counters). This cookie is specified
in the CoT.
int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr);
This API sets a new counter value. The cookie may be
used to select the counter to be updated.
An implementation of these new APIs for ARM platforms is also
provided. The values are obtained from the Trusted Non-Volatile
Counters peripheral. The cookie is used to pass the extension OID.
This OID may be interpreted by the platform to know which counter
must return. On Juno, The trusted and non-trusted counter values
have been tied to 31 and 223, respectively, and cannot be modified.
** IMPORTANT **
THIS PATCH BREAKS THE BUILD WHEN TRUSTED_BOARD_BOOT IS ENABLED. THE
NEW PLATFORM APIs INTRODUCED IN THIS PATCH MUST BE IMPLEMENTED IN
ORDER TO SUCCESSFULLY BUILD TF.
Change-Id: Ic943b76b25f2a37f490eaaab6d87b4a8b3cbc89a
Juan Castillo
committed
on 31 Mar 2016
|
2016-03-11 |
Add "size" function to IO memmap device driver
...
Hence memmap device can be used to load an image without being wrapped in a
FIP.
Fixes arm-software/tf-issues#371
Signed-off-by: Gerald Lejeune <gerald.lejeune@st.com>
Gerald Lejeune
committed
on 11 Mar 2016
|