drivers: marvell: add CCU driver API for window state checking ...

Add ccu_is_win_enabled() API for checking the CCU window
state using AP and window indexes.

Change-Id: Ib955a2cac28b2729b0a763f3bbbea28b476a2fe4
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

drivers: marvell: align and extend llc macros ...

Make all LLC-related macros to start with the same prefix
Add more LLC control registers definitions
This patch is a preparation step for LLC SRAM support

Change-Id: I0a4f0fc83e8ef35be93dd239a85f2a9f88d1ab19
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

marvell: comphy: initialize common phy selector for AP mode ...

Configuring common phy selector which was missing for AP mode.

Change-Id: I15be1ba50b8aafe9094734abec139d72c18bb224
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

marvell: comphy: update rx_training procedure ...

1) Relay only on rx training, remove parts responsible for tx training
(trx training).
2) Add extra steps e.g. preconfigure FFE before starting training.
3) Remove some unnecessary steps like RRBS31 loopback setting which
shouldn't be relevant for tx_training.

Change-Id: Ib1e8567714f9ce33578186a262c339aa4b1c51f2
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

Merge changes I80316689,I23cac4fb,If911e7de,I169ff358,I4e040cd5, ... into integration ...

* changes:
  ddr: a80x0: add DDR 32-bit ECC mode support
  ble: ap807: improve PLL configuration sequence
  ble: ap807: clean-up PLL configuration sequence
  ddr: a80x0: add DDR 32-bit mode support
  plat: marvell: mci: perform mci link tuning for all mci interfaces
  plat: marvell: mci: use more meaningful name for mci link tuning
  plat: marvell: a8k: remove wrong or unnecessary comments
  plat: marvell: ap807: enable snoop filter for ap807
  plat: marvell: ap807: update configuration space of each CP
  plat: marvell: ap807: use correct address for MCIx4 register
  plat: marvell: add support for PLL 2.2GHz mode
  plat: marvell: armada: make a8k_common.mk and mss_common.mk more generic
  marvell: armada: add extra level in marvell platform hierarchy

tbbr: add chain of trust for Secure Partitions ...

with sha 44f1aa8, support for Silicon Provider(SiP) owned Secure
Partition(SP) was added for dualroot CoT. This patch extends this
support for tbbr CoT.

Earlier tbbr CoT for SPs was left to avoid adding new image types in
TBBR which could possibly be seen as deviation from specification.
But with further discussions it is understood that TBBR being a
*minimal* set of requirements that can be extended as long as we don't
violate any of the musts, which is the case with adding SP support.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I1b9e3ebdd7d653f1fd4cc3bd910a69871b55ecbb

Merge "GICv3: GIC-600: Detect GIC-600 at runtime" into integration

GICv3: GIC-600: Detect GIC-600 at runtime ...

The only difference between GIC-500 and GIC-600 relevant to TF-A is the
differing power management sequence.
A certain GIC implementation is detectable at runtime, for instance by
checking the IIDR register. Let's add that test before initiating the
GIC-600 specific sequence, so the code can be used on both GIC-600 and
GIC-500 chips alike, without deciding on a GIC chip at compile time.

This means that the GIC-500 "driver" is now redundant. To allow minimal
platform support, add a switch to disable GIC-600 support.

Change-Id: I17ea97d9fb05874772ebaa13e6678b4ba3415557
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

dualroot: add chain of trust for secure partitions ...

A new certificate "sip-sp-cert" has been added for Silicon Provider(SiP)
owned Secure Partitions(SP). A similar support for Platform owned SP can
be added in future. The certificate is also protected against anti-
rollback using the trusted Non-Volatile counter.

To avoid deviating from TBBR spec, support for SP CoT is only provided
in dualroot.
Secure Partition content certificate is assigned image ID 31 and SP
images follows after it.

The CoT for secure partition look like below.
+------------------+       +-------------------+
| ROTPK/ROTPK Hash |------>| Trusted Key       |
+------------------+       | Certificate       |
                           | (Auth Image)      |
                          /+-------------------+
                         /                   |
                        /                    |
                       /                     |
                      /                      |
                     L                       v
+------------------+       +-------------------+
| Trusted World    |------>| SiP owned SPs     |
| Public Key       |       | Content Cert      |
+------------------+       | (Auth Image)      |
                        /   +-------------------+
                       /                      |
                      /                      v|
+------------------+ L     +-------------------+
| SP_PKG1 Hash     |------>| SP_PKG1           |
|                  |       | (Data Image)      |
+------------------+       +-------------------+
        .                           .
        .                           .
        .                           .
+------------------+       +-------------------+
| SP_PKG8 Hash     |------>| SP_PKG8           |
|                  |       | (Data Image)      |
+------------------+       +-------------------+

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ia31546bac1327a3e0b5d37e8b99c808442d5e53f

ble: ap807: improve PLL configuration sequence ...

Update PLL configuration according to HW team guidelines.

Change-Id: I23cac4fb4a638e7416965a5399ce6947e08d0711
Signed-off-by: Alex Leibovich <alexl@marvell.com>

ble: ap807: clean-up PLL configuration sequence ...

Remove pll powerdown from pll configuration sequence to improve
stability. Remove redundant cases, which no longer exist.
Also get rid of irrelevant definition of CPU_2200_DDR_1200_RCLK_1200,
which is not used by 806/807.

Change-Id: If911e7dee003dfb9a42fafd7ffe34662f026fd23
Signed-off-by: Alex Leibovich <alexl@marvell.com>

plat: marvell: mci: perform mci link tuning for all mci interfaces ...

This commit introduces two changes:
- remove hardcoded references to mci0 from the driver
- perform mci optimization for all mci interfaces

It fixes performance issues observed on cn9132 CP2.

Change-Id: I4e040cd54ff95c9134035ac89b87d8feb28e9eba
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

plat: marvell: mci: use more meaningful name for mci link tuning ...

The mci_initialize function name was misleading. The function itself
doesn't initialize MCI in general but performs MCI link tuning for
performance improvement.

Change-Id: I13094ad2235182a14984035bbe58013ebde84a7e
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

plat: marvell: ap807: update configuration space of each CP ...

By default all external CPs start with configuration address space set to
0xf200_0000. To overcome this issue, go in the loop and initialize the
CP one by one, using temporary window configuration which allows to access
each CP and update its configuration space according to decoding
windows scheme defined for each platform.

In case of cn9130 after this procedure bellow addresses will be used:
CP0 - f2000000
CP1 - f4000000
CP2 - f6000000

When the re-configuration is done there is need to restore previous
decoding window configuration(init_io_win).

Change-Id: I1a652bfbd0bf7106930a7a4e949094dc9078a981
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

plat: marvell: ap807: use correct address for MCIx4 register ...

The AP807 uses different register offset for MCIx4 register, reflect it
in the code.

Change-Id: Ic7e44fede3c69083e8629741e7c440b1ae08c35f
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

plat: marvell: add support for PLL 2.2GHz mode ...

Change-Id: Icb8fe14417665d6aadd5a5ee2b77547b4ef78773
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

marvell: armada: add extra level in marvell platform hierarchy ...

This commit is a preparation for upcoming support for OcteonTX and
OcteonTX2 product families. Armada platform related files (docs,
plat, include/plat) are moved to the new "armada" sub-folder.

Change-Id: Icf03356187078ad6a2e56c9870992be3ca4c9655
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

Merge "marvell: drivers: mochi: specify stream ID for SD/MMC" into integration

drivers: introduce ST ETZPC driver ...

ETZPC stands for Extended TrustZone Protection Controller. It is a
resource conditional access device. It is mainly based on Arm TZPC.

ST ETZPC exposes memory mapped DECPROT cells to set access permissions
to SoC peripheral interfaces as I2C, SPI, DDR controllers, and some
of the SoC internal memories.

ST ETZPC exposes memory mapped TZMA cells to set access permissions
to some SoC internal memories.

Change-Id: I47ce20ffcfb55306dab923153b71e1bcbe2a5570
Co-developed-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

marvell: drivers: mochi: specify stream ID for SD/MMC ...

This patch enables the stream ID for the SD/MMC
controllers via dedicated unit register. Thanks to this
change it is possible to configure properly the
IOMMU in OS and use the SD/MMC interface in a guest
Virtual Machine.

Change-Id: I99cbd2c9882eb558ba01405d3d8a3e969f06e082
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Signed-off-by: Tomasz Nowicki <tn@semihalf.com>

Merge "drivers: stm32_reset adapt interface to timeout argument" into integration

drivers: stm32_reset adapt interface to timeout argument ...

Changes stm32mp1 reset driver to API to add a timeout argument
to stm32mp_reset_assert() and stm32mp_reset_deassert() and
a return value.

With a supplied timeout, the functions wait the target reset state
is reached before returning. With a timeout of zero, the functions
simply load target reset state in SoC interface and return without
waiting.

Helper functions stm32mp_reset_set() and stm32mp_reset_release()
use a zero timeout and return without a return code.

This change updates few stm32 drivers and plat/stm32mp1 blé_plat_setup.c
accordingly without any functional change.
functional change.

Change-Id: Ia1a73a15125d3055fd8739c125b70bcb9562c27f
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

Merge "drivers: stm32mp1 clocks: fix debug trace on clock enable/disable" into integration

Merge "drivers: stm32mp1 clocks: enable system clocks during initialization" into integration

Merge "drivers: stm32mp1 clocks: prevent crash on always on clocks" into integration

Merge "drivers: stm32mp1 clocks: add RTC as a gateable clock" into integration

Merge "drivers: stm32mp1 clocks: support shifted clock selector bit masks" into integration

Merge "drivers: stm32mp1 clocks: allow tree lookup for several system clocks" into integration

Cleanup the code for TBBR CoT descriptors ...

CoT used for BL1 and BL2 are moved to tbbr_cot_bl1.c
and tbbr_cot_bl2.c respectively.
Common CoT used across BL1 and BL2 are moved to
tbbr_cot_common.c.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I2252ac8a6960b3431bcaafdb3ea4fb2d01b79cf5

drivers: stm32mp1 clocks: fix debug trace on clock enable/disable ...

Adds missing terminal new line character '\n' to debug traces,
fix format as index is an unsigned value and use present tense rather
than past tense in the printed message.

Change-Id: I88c06ef4d3a11d97ff8e96875a3dd0f58a3c98b6
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>