LuminaSensum/arm-trusted-firmware

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LuminaSensum / arm-trusted-firmware

2019-09-12	6a415a5 Browse files » Remove RSA PKCS#1 v1.5 support from cert_tool ... Support for PKCS#1 v1.5 was deprecated in SHA 1001202 and fully removed in SHA fe199e3, however, cert_tool is still able to generate certificates in that form. This patch fully removes the ability for cert_tool to generate these certificates. Additionally, this patch also fixes a bug where the issuing certificate was a RSA and the issued certificate was EcDSA. In this case, the issued certificate would be signed using PKCS#1 v1.5 instead of RSAPSS per PKCS#1 v2.1, preventing TF-A from verifying the image signatures. Now that PKCS#1 v1.5 support is removed, all certificates that are signed with RSA now use the more modern padding scheme. Change-Id: Id87d7d915be594a1876a73080528d968e65c4e9a Signed-off-by: Justin Chadwell <justin.chadwell@arm.com> Justin Chadwell committed on 12 Sep 2019
	f29213d Browse files » Add documentation for new KEY_SIZE option ... This patch adds documentation for the new KEY_SIZE build option that is exposed by cert_create, and instructions on how to use it. Change-Id: I09b9b052bfdeeaca837e0f0026e2b01144f2472c Signed-off-by: Justin Chadwell <justin.chadwell@arm.com> Justin Chadwell committed on 12 Sep 2019
	dfe0f4c Browse files » Add cert_create tool support for RSA key sizes ... cert_tool is now able to accept a command line option for specifying the key size. It now supports the following options: 1024, 2048 (default), 3072 and 4096. This is also modifiable by TFA using the build flag KEY_SIZE. Change-Id: Ifadecf84ade3763249ee8cc7123a8178f606f0e5 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com> Justin Chadwell committed on 12 Sep 2019
	aacff74 Browse files » Support larger RSA key sizes when using MBEDTLS ... Previously, TF-A could not support large RSA key sizes as the configuration options passed to MBEDTLS prevented storing and performing calculations with the larger, higher-precision numbers required. With these changes to the arguments passed to MBEDTLS, TF-A now supports using 3072 (3K) and 4096 (4K) keys in certificates. Change-Id: Ib73a6773145d2faa25c28d04f9a42e86f2fd555f Signed-off-by: Justin Chadwell <justin.chadwell@arm.com> Justin Chadwell committed on 12 Sep 2019
	2fc6ffc Browse files » Merge "libc: fix sparse warning for __assert()" into integration Soby Mathew authored on 12 Sep 2019 TrustedFirmware Code Review committed on 12 Sep 2019
	4210af0 Browse files » Merge "doc: Updated user guide with new Mbed TLS version number" into integration Soby Mathew authored on 12 Sep 2019 TrustedFirmware Code Review committed on 12 Sep 2019
	8911a32 Browse files » Merge "intel: agilex: Fix psci power domain off" into integration Soby Mathew authored on 12 Sep 2019 TrustedFirmware Code Review committed on 12 Sep 2019
	91624b7 Browse files » Merge changes from topic "jc/mte_enable" into integration ... * changes: Add documentation for CTX_INCLUDE_MTE_REGS Enable MTE support in both secure and non-secure worlds Soby Mathew authored on 12 Sep 2019 TrustedFirmware Code Review committed on 12 Sep 2019
	5beeec7 Browse files » Merge "plat: xilinx: zynqmp: Initialize IPI table from zynqmp_config_setup()" into integration Soby Mathew authored on 12 Sep 2019 TrustedFirmware Code Review committed on 12 Sep 2019
	18eb002 Browse files » Merge "Zeus: apply the MSR SSBS instruction" into integration Soby Mathew authored on 12 Sep 2019 TrustedFirmware Code Review committed on 12 Sep 2019
	684b3a0 Browse files » Merge "Add UBSAN support and handlers" into integration Soby Mathew authored on 12 Sep 2019 TrustedFirmware Code Review committed on 12 Sep 2019
	f38e518 Browse files » Merge changes I072c0f61,I798401f4,I9648ef55,I7225d9fa,Ife682288, ... into integration ... * changes: rcar_gen3: drivers: ddr_b: Update DDR setting for H3, M3, M3N rcar_gen3: drivers: qos: update QoS setting rcar_gen3: drivers: ddr_b: Fix checkpatch errors in headers rcar_gen3: drivers: ddr_b: Fix line-over-80s rcar_gen3: drivers: ddr_b: Further checkpatch cleanups rcar_gen3: drivers: ddr_b: Clean up camel case rcar_get3: drivers: ddr_b: Basic checkpatch fixes rcar_get3: drivers: ddr: Partly unify register macros between DDR A and B rcar_get3: drivers: ddr: Clean up common code Soby Mathew authored on 12 Sep 2019 TrustedFirmware Code Review committed on 12 Sep 2019
	9af73b3 Browse files » Merge changes from topic "amlogic-refactoring" into integration ... * changes: amlogic: Fix includes order amlogic: Fix header guards amlogic: Fix prefixes in the SoC specific files amlogic: Fix prefixes in the PM code amlogic: Fix prefixes in the SCPI related code amlogic: Fix prefixes in the MHU code amlogic: Fix prefixes in the SIP/SVC code amlogic: Fix prefixes in the thermal driver amlogic: Fix prefixes in the private header file amlogic: Fix prefixes in the efuse driver amlogic: Fix prefixes in the platform macros file amlogic: Fix prefixes in the helpers file amlogic: Rework Makefiles amlogic: Move the SIP SVC code to common directory amlogic: Move topology file to common directory amlogic: Move thermal code to common directory amlogic: Move MHU code to common directory amlogic: Move efuse code to common directory amlogic: Move platform macros assembly file to common directory amlogic: Introduce unified private header file amlogic: Move SCPI code to common directory amlogic: Move the SHA256 DMA driver to common directory amlogic: Move assembly helpers to common directory amlogic: Introduce directory parameters in the makefiles meson: Rename platform directory to amlogic Soby Mathew authored on 12 Sep 2019 TrustedFirmware Code Review committed on 12 Sep 2019
	afac968 Browse files » intel: agilex: Fix psci power domain off ... Disable gic cpu interface for powered down cpu. This patch also removes core reset during power off as core reset will be done during power on Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I2ca96d876b6e71e56d24a9a7e184b6d6226b8673 Hadi Asyrafi committed on 12 Sep 2019
2019-09-11	b562187 Browse files » amlogic: Fix includes order ... As part of the code refactoring fix the order of the include files across all the source files. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Ice72f687cc26ee881a9051168149467688100cfb Carlo Caione committed on 11 Sep 2019
	421b67b Browse files » amlogic: Fix header guards ... Make the header guards more generic and contextually remove the GXBB_BL31_PLAT_PARAM_VAL value that is unused on the GXL platform. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I842fa2e084e71280ae17b39c67877e844821a171 Carlo Caione committed on 11 Sep 2019
	749b334 Browse files » Merge "mbedtls: use #include <...> instead of "..."" into integration Soby Mathew authored on 11 Sep 2019 TrustedFirmware Code Review committed on 11 Sep 2019
	07f979b Browse files » Zeus: apply the MSR SSBS instruction ... Zeus supports the SSBS mechanism and also the new MSR instruction to immediately apply the mitigation. Hence, the new instruction is utilised in the Zeus-specific reset function. Change-Id: I962747c28afe85a15207a0eba4146f9a115b27e7 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> John Tsichritzis committed on 11 Sep 2019
	1f46197 Browse files » Add UBSAN support and handlers ... This patch adds support for the Undefined Behaviour sanitizer. There are two types of support offered - minimalistic trapping support which essentially immediately crashes on undefined behaviour and full support with full debug messages. The full support relies on ubsan.c which has been adapted from code used by OPTEE. Change-Id: I417c810f4fc43dcb56db6a6a555bfd0b38440727 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com> Justin Chadwell committed on 11 Sep 2019
2019-09-10	f906a44 Browse files » libc: fix sparse warning for __assert() ... Sparse warns this: lib/libc/assert.c:29:6: error: symbol '__assert' redeclared with different type (originally declared at include/lib/libc/assert.h:36) - different modifiers Add __dead2 to match the header declaration and C definition. I also changed '__dead2 void' to 'void __dead2' for the consistency with other parts. Change-Id: Iefa4f0e787c24fa7e7e499d2e7baf54d4deb49ef Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Masahiro Yamada committed on 10 Sep 2019
	705bed5 Browse files » plat: xilinx: zynqmp: Initialize IPI table from zynqmp_config_setup() ... Common ipi_table needs to be initialized before using any IPI command (i.e send/receive). Move zynqmp ipi config table initialization from sip_svc_setup() to zynqmp_config_setup(). Change-Id: Ic8aaa0728a43936cd4c6e1ed590e01ba8f0fbf5b Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Jolly Shah committed on 10 Sep 2019
	0289ab9 Browse files » Merge changes from topic "yg/stm32mp1_wdg_updates" into integration ... * changes: mmc: stm32_sdmmc2: correctly manage block size mmc: stm32_sdmmc2: manage max-frequency property from DT stm32mp1: move check_header() to common code stm32mp1: keep console during runtime stm32mp1: sp_min: initialize MMU and cache earlier stm32mp1: add support for LpDDR3 stm32mp1: use a common function to check spinlock is available clk: stm32mp: enable RTCAPB clock for dual-core chips stm32mp1: check if the SoC is single core stm32mp1: print information about board stm32mp1: print information about SoC stm32mp1: add watchdog support Soby Mathew authored on 10 Sep 2019 TrustedFirmware Code Review committed on 10 Sep 2019
2019-09-09	88d493f Browse files » Add documentation for CTX_INCLUDE_MTE_REGS ... A new build flag, CTX_INCLUDE_MTE_REGS, has been added; this patch adds documentation for it in the User Guide along with instructions of what different values mean. Change-Id: I430a9c6ced06b1b6be317edbeff4f5530e30f63a Signed-off-by: Justin Chadwell <justin.chadwell@arm.com> Justin Chadwell committed on 9 Sep 2019
2019-09-09	9dd9438 Browse files » Enable MTE support in both secure and non-secure worlds ... This patch adds support for the new Memory Tagging Extension arriving in ARMv8.5. MTE support is now enabled by default on systems that support at EL0. To enable it at ELx for both the non-secure and the secure world, the compiler flag CTX_INCLUDE_MTE_REGS includes register saving and restoring when necessary in order to prevent register leakage between the worlds. Change-Id: I2d4ea993d6b11654ea0d4757d00ca20d23acf36c Signed-off-by: Justin Chadwell <justin.chadwell@arm.com> Justin Chadwell committed on 9 Sep 2019
2019-09-05	9158854 Browse files » amlogic: Fix prefixes in the SoC specific files ... Remove the GXBB prefix where needed and add SoC specific prefixes for GXBB/GXL. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Ic3eb3a77ca2d9c779a9dee5cee786e9c16ecdb27 Carlo Caione committed on 5 Sep 2019
	0e1d789 Browse files » amlogic: Fix prefixes in the PM code ... Remove the GXBB prefix from the code in the common directory and add SoC-specific prefixes in the SoC specific code. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Ic983ef70b0ef23f95088dd8df488d8c42c3bc030 Carlo Caione committed on 5 Sep 2019
	9a5616f Browse files » amlogic: Fix prefixes in the SCPI related code ... Add a new aml_* prefix to the SCPI related function calls. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I697812ac1c0df28cbb639a1dc3e838f1107fb739 Carlo Caione committed on 5 Sep 2019
	cbaad53 Browse files » amlogic: Fix prefixes in the MHU code ... Make the MHU code AML specific adding a new aml_* prefix and remove the GXBB prefix from the register names. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I8f20918e29f08542bd71bd679f88e65b4efaa7d2 Carlo Caione committed on 5 Sep 2019
	381b901 Browse files » amlogic: Fix prefixes in the SIP/SVC code ... All the SIP/SVC related code is currently the same between GXL and GXBB. Rename function names and register names to avoid hardcoding the GXBB prefix. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I7e58ab68489df8d4762663fc01fb64e6899cc8bf Carlo Caione committed on 5 Sep 2019
	73f6d05 Browse files » amlogic: Fix prefixes in the thermal driver ... No need to have a special SoC-specific prefix. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I0da543e7d92d56604e79440a98027ffd9a2eaa59 Carlo Caione committed on 5 Sep 2019