GIC-600: Fix power up sequence ...

Arm's GIC-600 features a Power Register (GICR_PWRR),
which needs to be programmed to enable redistributor
operation. Section 3.6.1 in the GIC-600 TRM describes
the power-up and power-down sequence in pseudo code,
which deviates from the current TF-A implementation
in drivers/arm/gic/v3/gic600.c.
For powering on a redistributor, the pseudo code suggests
to loop over the whole sequence (check for transition,
write request bit) instead of just looping over the
ready bit read as TF-A does in gic600_pwr_on().
This patch fixes GIC-600 power up sequence according
to the TRM.

Change-Id: I445c480e96ba356b69a2d8e5308ffe6c0a97f45b
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

Merge "Coding guideline suggest not to use unsigned long" into integration

Merge "TF-A: Fix non-standard frequency issue in udelay" into integration

TF-A: Fix non-standard frequency issue in udelay ...

Previous implementation of timers assumed that clk_div has pretty
representation in MHz (10MHz, 100MHz, etc). Unusual frequencies
(99.99MHz) were causing assertion error and made udelay unusable.

Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: Ic915fff224369d113fd9f8edbcfff169fca8beac

Merge "docs: Add Cortex-Hercules/HerculesAE CPU support" into integration

docs: Add Cortex-Hercules/HerculesAE CPU support ...

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ia1ff13be1308e63c2854d2b6e5f6651750186abe

Merge changes from topic "tegra-downstream-092319" into integration ...

* changes:
  Tegra194: add macros for security carveout configuration registers
  Tegra194: add 'TEGRA_TMRUS_SIZE' macro
  Tegra194: Fix TEGRA186_SMMU_CTX_SIZE
  Tegra194: Dont run MCE firmware on Emulation
  Tegra194: remove GPU, MPCORE and PTC registers from streamid list
  Tegra194: Support SMC64 encoding for MCE calls
  Tegra194: Enable MCE driver
  Tegra194: enable SMMU
  Tegra194: add support for multiple SMMU devices
  Tegra194: add SMMU and mc_sid support
  Tegra194: psci: support for 64-bit TZDRAM base
  Tegra194: base commit for the platform
  Revert "Tegra: Add support for fake system suspend"

Merge "Fix white space errors + remove #if defined" into integration

Coding guideline suggest not to use unsigned long ...

`unsigned long` should be replaced to
1. `unsigned int` or `unsigned long long` - If fixed,
based on the architecture AArch32 or AArch64
2. `u_register_t` - If it is supposed to be 32-bit
wide in AArch32 and 64-bit wide in AArch64.

Translation descriptors are always 32-bit wide, here
`uint32_t` is used to describe the `exact size` of
translation descriptors instead of `unsigned int` which
guarantees minimum 32-bits

Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I6a2af2e8b3c71170e2634044e0b887f07a41677e

Merge "plat/arm: Re-enable PIE when RESET_TO_BL31=1" into integration

Merge "TF-A Documentation: Update Security Advisory TFV-5 (CVE-2017-15031)" into integration

Merge "Disable stack protection explicitly" into integration

Merge "n1sdp: setup multichip gic routing table" into integration

Merge changes from topic "gic600_multichip" into integration ...

* changes:
  gic/gic600: add support for multichip configuration
  plat/arm/gicv3: add support for probing multiple GIC Redistributor frames

n1sdp: setup multichip gic routing table ...

N1SDP supports multichip configuration wherein n1sdp boards are
connected over high speed coherent CCIX link, for now only dual-chip
is supported.

Whether or not multiple chips are present is dynamically probed by
SCP firmware and passed on to TF-A, routing table will be set up
only if multiple chips are present.

Initialize GIC-600 multichip operation by overriding the default GICR
frames with array of GICR frames and setting the chip 0 as routing
table owner.

Change-Id: Ida35672be4bbf4c517469a5b330548d75e593ff2
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

gic/gic600: add support for multichip configuration ...

Add support to configure GIC-600's multichip routing table registers.
Introduce a new gic600 multichip structure in order to support platforms
to pass their GIC-600 multichip information such as routing table owner,
SPI blocks ownership.

This driver is currently experimental and the driver api may change in
the future.

Change-Id: Id409d0bc07843e271ead3fc2f6e3cb38b317878d
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>

plat/arm: Re-enable PIE when RESET_TO_BL31=1 ...

Earlier PIE support was enabled for all arm platforms when
RESET_TO_BL31=1, but later on it was restricted only to FVP with patch
SHA d4580d17 because of n1sdp platform.

Now it has been verified that PIE does work for n1sdp platform also, so
enabling it again for all arm platforms.

Change-Id: I05ad4f1775ef72e7cb578ec9245cde3fbce971a5
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

plat/arm/gicv3: add support for probing multiple GIC Redistributor frames ...

ARM platform can have a non-contiguous GICR frames. For instance, a
multi socket platform can have two or more GIC Redistributor frames
which are 4TB apart. Hence it is necessary for the `gicv3_rdistif_probe`
function to probe all the GICR frames available in the platform.

Introduce `plat_arm_override_gicr_frames` function which platforms can
use to override the default gicr_frames which holds the GICR base
address of the primary cpu.

Change-Id: I1f537b0d871a679cb256092944737f2e55ab866e
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>

TF-A Documentation: Update Security Advisory TFV-5 (CVE-2017-15031) ...

This patch updates description of Security Advisory TFV-5.

Change-Id: Ieaee0b51a79843345b1aca5d0e20c4964beb3c95
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

Merge "SMMUv3:Changed retry loop to delay timer(GENFW-3329)" into integration

SMMUv3:Changed retry loop to delay timer(GENFW-3329) ...

Instead of retry polling, timer of 1ms is used to poll

Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I7e028dc68138d2888e3cf0cbed744f5e6bc6ff42

Merge changes I75799fd4,I4781dc6a into integration ...

* changes:
  n1sdp: update platform macros for dual-chip setup
  n1sdp: introduce platform information SDS region

n1sdp: update platform macros for dual-chip setup ...

N1SDP supports multichip configuration wherein n1sdp boards are
connected over high speed coherent CCIX link  for now only dual-chip is
supported.

A single instance of TF-A runs on master chip which should be aware of
slave chip's CPU and memory topology.

This patch updates platform macros to include remote chip's information
and also ensures that a single version of firmware works for both single
and dual-chip setup.

Change-Id: I75799fd46dc10527aa99585226099d836c21da70
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

n1sdp: introduce platform information SDS region ...

Platform information structure holds information about platform's DDR
size(local/remote) which will be used to zero out the memory before
enabling the ECC capability as well as information about multichip
setup. Multichip and remote DDR information can only be probed in SCP,
SDS region will be used by TF-A to get this information at boot up.

This patch introduces a new SDS to store platform information, which is
populated dynamically by SCP Firmware.previously used mem_info SDS is
also made part of this structure itself.

The platform information is also passed to BL33 by copying it to Non-
Secure SRAM.

Change-Id: I4781dc6a7232c3c0a3219b164d943ce9e3e469ee
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

Merge "doc: Fix syntax erros in I/O storage layer plantuml diagrams" into integration

Merge "ti: k3: common: Add PIE support" into integration

ti: k3: common: Add PIE support ...

Running TF-A from non-standard location such as DRAM is useful for some
SRAM heavy use-cases. Allow the TF-A binary to be executed from an
arbitrary memory location.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Icd97926e4d97f37d7cde4a92758a52f57d569111

doc: Fix syntax erros in I/O storage layer plantuml diagrams ...

Some of the plantuml diagrams in the I/O storage abstraction layer
documentation are absent from the rendered version of the porting
guide. The build log (see [1] for example) reports a syntax error in
these files. This is due to the usage of the 'order' keyword on the
participants list, which does not seem to be supported by the version
of plantuml installed on the ReadTheDocs server.

Fix these syntax errors by removing the 'order' keyword altogether. We
simply rely on the participants being declared in the desired order,
which will be the order of display, according to the plantuml
documentation.

[1] https://readthedocs.org/api/v2/build/9870345.txt

Change-Id: Ife35c74cb2f1dac28bda07df395244639a8d6a2b
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Merge "plat/arm: use Aff3 bits also to validate mpidr" into integration

Tegra194: add macros for security carveout configuration registers ...

This patch adds macros defining the generalised security carveout
registers. These macros help us program the TZRAM carveout access
and the Video Protect Clear carveout access.

Change-Id: I8f7b24b653fdb702fb57a4097801cb3eae050294
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>