2014-08-19 |
Rework state management in the PSCI implementation
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This patch pulls out state management from the affinity level specific handlers
into the top level functions specific to the operation
i.e. psci_afflvl_suspend(), psci_afflvl_on() etc.
In the power down path this patch will allow an affinity instance at level X to
determine the state that an affinity instance at level X+1 will enter before the
level specific handlers are called. This will be useful to determine whether a
CPU is the last in the cluster during a suspend/off request and so on.
Similarly, in the power up path this patch will allow an affinity instance at
level X to determine the state that an affinity instance at level X+1 has
emerged from, even after the level specific handlers have been called. This will
be useful in determining whether a CPU is the first in the cluster during a
on/resume request and so on.
As before, while powering down, state is updated before the level specific
handlers are invoked so that they can perform actions based upon their target
state. While powering up, state is updated after the level specific handlers have
been invoked so that they can perform actions based upon the state they emerged
from.
Change-Id: I40fe64cb61bb096c66f88f6d493a1931243cfd37
Achin Gupta
authored
on 27 Jul 2014
Soby Mathew
committed
on 19 Aug 2014
|
Add PSCI service specific per-CPU data
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This patch adds a structure defined by the PSCI service to the per-CPU data
array. The structure is used to save the 'power_state' parameter specified
during a 'cpu_suspend' call on the current CPU. This parameter was being saved
in the cpu node in the PSCI topology tree earlier.
The existing API to return the state id specified during a PSCI CPU_SUSPEND call
i.e. psci_get_suspend_stateid(mpidr) has been renamed to
psci_get_suspend_stateid_by_mpidr(mpidr). The new psci_get_suspend_stateid() API
returns the state id of the current cpu.
The psci_get_suspend_afflvl() API has been changed to return the target affinity
level of the current CPU. This was specified using the 'mpidr' parameter in the
old implementation.
The behaviour of the get_power_on_target_afflvl() has been tweaked such that
traversal of the PSCI topology tree to locate the affinity instance node for the
current CPU is done only in the debug build as it is an expensive operation.
Change-Id: Iaad49db75abda471f6a82d697ee6e0df554c4caf
Achin Gupta
authored
on 25 Jul 2014
Soby Mathew
committed
on 19 Aug 2014
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Add macro to flush per-CPU data
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This patch adds a macro which will flush the contents of the specified member of
the per-CPU data structure to the PoC. This is required to enable an update of a
per-CPU data member to be visible to all observers.
Change-Id: I20e0feb9b9f345dc5a1162e88adc7956a7ad7a64
Achin Gupta
authored
on 25 Jul 2014
Soby Mathew
committed
on 19 Aug 2014
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Merge pull request #191 from danh-arm/jc/tf-issues/218
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Add support for PSCI SYSTEM_OFF and SYSTEM_RESET APIs v2
danh-arm
committed
on 19 Aug 2014
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Add support for PSCI SYSTEM_OFF and SYSTEM_RESET APIs
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This patch adds support for SYSTEM_OFF and SYSTEM_RESET PSCI
operations. A platform should export handlers to complete the
requested operation. The FVP port exports fvp_system_off() and
fvp_system_reset() as an example.
If the SPD provides a power management hook for system off and
system reset, then the SPD is notified about the corresponding
operation so it can do some bookkeeping. The TSPD exports
tspd_system_off() and tspd_system_reset() for that purpose.
Versatile Express shutdown and reset methods have been removed
from the FDT as new PSCI sys_poweroff and sys_reset services
have been added. For those kernels that do not support yet these
PSCI services (i.e. GICv3 kernel), the original dtsi files have
been renamed to *-no_psci.dtsi.
Fixes ARM-software/tf-issues#218
Change-Id: Ic8a3bf801db979099ab7029162af041c4e8330c8
Juan Castillo
authored
on 12 Aug 2014
Dan Handley
committed
on 19 Aug 2014
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Merge pull request #189 from achingupta/ag/tf-issues#153
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Unmask SError interrupt and clear SCR_EL3.EA bit
Dan Handley
committed
on 19 Aug 2014
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Merge pull request #181 from danh-arm/dh/tsp_fvp_dependency
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Move TSP private declarations into separate header
Clarify platform porting interface to TSP
Dan Handley
committed
on 19 Aug 2014
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Clarify platform porting interface to TSP
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* Move TSP platform porting functions to new file:
include/bl32/tsp/platform_tsp.h.
* Create new TSP_IRQ_SEC_PHY_TIMER definition for use by the generic
TSP interrupt handling code, instead of depending on the FVP
specific definition IRQ_SEC_PHY_TIMER.
* Rename TSP platform porting functions from bl32_* to tsp_*, and
definitions from BL32_* to TSP_*.
* Update generic TSP code to use new platform porting function names
and definitions.
* Update FVP port accordingly and move all TSP source files to:
plat/fvp/tsp/.
* Update porting guide with above changes.
Note: THIS CHANGE REQUIRES ALL PLATFORM PORTS OF THE TSP TO
BE UPDATED
Fixes ARM-software/tf-issues#167
Change-Id: Ic0ff8caf72aebb378d378193d2f017599fc6b78f
Dan Handley
committed
on 19 Aug 2014
|
2014-08-15 |
Unmask SError interrupt and clear SCR_EL3.EA bit
...
This patch disables routing of external aborts from lower exception levels to
EL3 and ensures that a SError interrupt generated as a result of execution in
EL3 is taken locally instead of a lower exception level.
The SError interrupt is enabled in the TSP code only when the operation has not
been directly initiated by the normal world. This is to prevent the possibility
of an asynchronous external abort which originated in normal world from being
taken when execution is in S-EL1.
Fixes ARM-software/tf-issues#153
Change-Id: I157b996c75996d12fd86d27e98bc73dd8bce6cd5
Achin Gupta
committed
on 15 Aug 2014
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2014-08-14 |
Move TSP private declarations into separate header
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Move the TSP private declarations out of tsp.h and into a new
header, tsp_private.h. This clarifies the TSP interface to the TSPD.
Change-Id: I39af346eeba3350cadcac56c02d97a5cb978c28b
Dan Handley
committed
on 14 Aug 2014
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Merge pull request #187 from danh-arm/dh/refactor-drivers
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Refactor platform porting interface to drivers v2
danh-arm
committed
on 14 Aug 2014
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Simplify interface to TZC-400 driver
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The TZC-400 driver previously allowed the possibility of multiple
controller instances to be present in the same executable. This
was unnecessary since there will only ever be one instance.
This change simplifies the tzc_init() function to only take the
base address argument needed by implementation, conforming to the
driver initialization model of other drivers. It also hides some
of the implementation details that were previously exposed by the
API.
The FVP port has been updated accordingly.
THIS CHANGE REQUIRES ALL PLATFORM PORTS THAT USE THE TZC-400
DRIVER TO BE UPDATED
Fixes ARM-software/tf-issues#181
Change-Id: I7b721edf947064989958d8f457d6462d92e742c8
Dan Handley
committed
on 14 Aug 2014
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Move IO storage source to drivers directory
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Move the remaining IO storage source file (io_storage.c) from the
lib to the drivers directory. This requires that platform ports
explicitly add this file to the list of source files.
Also move the IO header files to a new sub-directory, include/io.
Change-Id: I862b1252a796b3bcac0d93e50b11e7fb2ded93d6
Dan Handley
committed
on 14 Aug 2014
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Remove redundant io_init() function
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The intent of io_init() was to allow platform ports to provide
a data object (io_plat_data_t) to the IO storage framework to
allocate into. The abstraction was incomplete because io_plat_data_t
uses a platform defined constant and the IO storage framework
internally allocates other arrays using platform defined constants.
This change simplifies the implementation by instantiating the
supporting objects in the IO storage framework itself. There is now
no need for the platform to call io_init().
The FVP port has been updated accordingly.
THIS CHANGE REQUIRES ALL PLATFORM PORTS THAT USE THE IO STORAGE
FRAMEWORK TO BE UDPATED.
Change-Id: Ib48ac334de9e538064734334c773f8b43df3a7dc
Dan Handley
committed
on 14 Aug 2014
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Remove platform dependency in CCI-400 driver
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* Create cci_init() function in CCI-400 driver to allow platform
to provide arguments needed by the driver (i.e. base address
and cluster indices for the ACE slave interfaces).
* Rename cci_(en|dis)able_coherency to
cci_(en|dis)able_cluster_coherency to make it clear that
the driver only enables/disables the coherency of CPU
clusters and not other devices connected to the CCI-400.
* Update FVP port to use new cci_init() function and remove
unnecessary CCI defintions from platform_def.h. Also rename
fvp_cci_setup() to fvp_cci_enable() to more clearly
differentiate between CCI initialization and enabling.
THIS CHANGE REQUIRES PLATFORM PORTS THAT USE THE CCI-400 DRIVER
TO BE UPDATED
Fixes ARM-software/tf-issues#168
Change-Id: I1946a51409b91217b92285b6375082619f607fec
Dan Handley
committed
on 14 Aug 2014
|
Merge pull request #184 from jcastillo-arm/jc/tf-issues/100
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FVP: make usage of Trusted DRAM optional at build time
danh-arm
committed
on 14 Aug 2014
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Merge pull request #186 from danh-arm/dh/fix-reset-to-bl31
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Fix reset to BL3-1 instructions in user guide
danh-arm
committed
on 14 Aug 2014
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FVP: make usage of Trusted DRAM optional at build time
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This patch groups the current contents of the Trusted DRAM region at
address 0x00_0600_0000 (entrypoint mailboxes and BL3-1 parameters) in
a single shared memory area that may be allocated to Trusted SRAM
(default) or Trusted DRAM at build time by setting the
FVP_SHARED_DATA_LOCATION make variable. The size of this shared
memory is 4096 bytes.
The combination 'Shared data in Trusted SRAM + TSP in Trusted DRAM'
is not currently supported due to restrictions in the maximum number
of mmu tables that can be created.
Documentation has been updated to reflect these changes.
Fixes ARM-software/tf-issues#100
Change-Id: I26ff04d33ce4cacf8d770d1a1e24132b4fc53ff0
Juan Castillo
committed
on 14 Aug 2014
|
2014-08-13 |
Fix reset to BL3-1 instructions in user guide
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Fix the instructions for resetting to the BL3-1 entrypoint in the
user guide. The BL3-1 and BL3-2 image locations changed in the fix
to ARM-software/tf-issues#117 (commit a1b6db6).
Fixes ARM-software/tf-issues#237
Change-Id: I764eb17c66034511efb984c0e7cfda29bd99198f
Dan Handley
committed
on 13 Aug 2014
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2014-08-12 |
Merge pull request #183 from danh-arm/dh/print_output2
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Add concept of console output log levels
Rationalize console log output
danh-arm
committed
on 12 Aug 2014
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Rationalize console log output
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Fix the following issues with the console log output:
* Make sure the welcome string is the first thing in the log output
(during normal boot).
* Prefix each message with the BL image name so it's clear which
BL the output is coming from.
* Ensure all output is wrapped in one of the log output macros so it can
be easily compiled out if necessary. Change some of the INFO() messages
to VERBOSE(), especially in the TSP.
* Create some extra NOTICE() and INFO() messages during cold boot.
* Remove all usage of \r in log output.
Fixes ARM-software/tf-issues#231
Change-Id: Ib24f7acb36ce64bbba549f204b9cde2dbb46c8a3
Dan Handley
committed
on 12 Aug 2014
|
Add concept of console output log levels
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Create new LOG_LEVEL build option, which controls the amount of
console output compiled into the build. This should be one of the
following:
0 (LOG_LEVEL_NONE)
10 (LOG_LEVEL_NOTICE)
20 (LOG_LEVEL_ERROR)
30 (LOG_LEVEL_WARNING)
40 (LOG_LEVEL_INFO)
50 (LOG_LEVEL_VERBOSE)
All log output up to and including the log level is compiled into the
build. The default value is 40 in debug builds and 20 in release
builds.
Complement the existing INFO, WARN and ERROR console output macros
with NOTICE and VERBOSE macros, which are conditionally compiled in
depending on the value of LOG_LEVEL.
Fixes ARM-software/tf-issues#232
Change-Id: I951e2f333e7b90fc4b1060741d9a6db699d5aa72
Dan Handley
committed
on 12 Aug 2014
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Merge pull request #182 from soby-mathew/sm/stack_optimize
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Reduce runtime stack size and add compilation macro for each BL stage
danh-arm
committed
on 12 Aug 2014
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Merge pull request #180 from jcastillo-arm/jc/tf-issues/207
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Move up to Linaro 14.07 toolchain
danh-arm
committed
on 12 Aug 2014
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FVP: apply new naming conventions to memory regions
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Secure ROM at address 0x0000_0000 is defined as FVP_TRUSTED_ROM
Secure RAM at address 0x0400_0000 is defined as FVP_TRUSTED_SRAM
Secure RAM at address 0x0600_0000 is defined as FVP_TRUSTED_DRAM
BLn_BASE and BLn_LIMIT definitions have been updated and are based on
these new memory regions.
The available memory for each bootloader in the linker script is
defined by BLn_BASE and BLn_LIMIT, instead of the complete memory
region.
TZROM_BASE/SIZE and TZRAM_BASE/SIZE are no longer required as part of
the platform porting.
FVP common definitions are defined in fvp_def.h while platform_def.h
contains exclusively (with a few exceptions) the definitions that are
mandatory in the porting guide. Therefore, platform_def.h now includes
fvp_def.h instead of the other way around.
Porting guide has been updated to reflect these changes.
Change-Id: I39a6088eb611fc4a347db0db4b8f1f0417dbab05
Juan Castillo
committed
on 12 Aug 2014
|
2014-08-11 |
Reduce the runtime stack size in BL stages.
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This patch separates the stack size for each BL stage and
reduces it after stack usage analysis was done.
Fixes ARM-software/tf-issues#200
Change-Id: I8edc6de2551b0a6788761d121937692b2149bb29
Soby Mathew
committed
on 11 Aug 2014
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Add compilation macro for each BL stage
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This patch defines a compile time macro for each boot loader stage
which allows compilation of code only for a specific stage.
Change-Id: I3a4068404cd3dc26d652556ca9ca7afea8dd28ef
Soby Mathew
committed
on 11 Aug 2014
|
2014-08-07 |
Move up to Linaro 14.07 toolchain
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Tests show a slight reduction in code size compared to 13.11.
User guide updated.
Fixes ARM-software/tf-issues#207
Change-Id: I9b80a5d7820cdfd443cac4d4b63f925b74a8c3a3
Juan Castillo
committed
on 7 Aug 2014
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2014-08-04 |
Merge pull request #179 from jcastillo-arm/jc/tf-issues/219
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Call platform_is_primary_cpu() only from reset handler
danh-arm
committed
on 4 Aug 2014
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Merge pull request #178 from soby-mathew/sm/optmize_el3_context
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Optimize EL3 register state stored in cpu_context structure
danh-arm
committed
on 4 Aug 2014
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