2015-09-14 |
Merge pull request #389 from vikramkanigiri/vk/css_rework
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Add more configurability options in ARM platform port code
Achin Gupta
committed
on 14 Sep 2015
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2015-09-11 |
Merge pull request #388 from achingupta/ag/spd_suspend_levels_v3
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Pass the target suspend level to SPD suspend hooks
Achin Gupta
committed
on 11 Sep 2015
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Separate CSS security setup from SOC security setup
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Currently, on ARM platforms(ex. Juno) non-secure access to specific
peripheral regions, config registers which are inside and outside CSS
is done in the soc_css_security_setup(). This patch separates the CSS
security setup from the SOC security setup in the css_security_setup().
The CSS security setup involves programming of the internal NIC to
provide access to regions inside the CSS. This is needed only in
Juno, hence Juno implements it in its board files as css_init_nic400().
Change-Id: I95a1fb9f13f9b18fa8e915eb4ae2f15264f1b060
Vikram Kanigiri
committed
on 11 Sep 2015
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Define the Non-Secure timer frame ID for ARM platforms
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On Juno and FVP platforms, the Non-Secure System timer corresponds
to frame 1. However, this is a platform-specific decision and it
shouldn't be hard-coded. Hence, this patch introduces
PLAT_ARM_NSTIMER_FRAME_ID which should be used by all ARM platforms
to specify the correct non-secure timer frame.
Change-Id: I6c3a905d7d89200a2f58c20ce5d1e1d166832bba
Vikram Kanigiri
committed
on 11 Sep 2015
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Re-factor definition of TZC-400 base address
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This patch replaces the `ARM_TZC_BASE` constant with `PLAT_ARM_TZC_BASE` to
support different TrustZone Controller base addresses across ARM platforms.
Change-Id: Ie4e1c7600fd7a5875323c7cc35e067de0c6ef6dd
Vikram Kanigiri
committed
on 11 Sep 2015
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2015-09-10 |
Pass the target suspend level to SPD suspend hooks
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In certain Trusted OS implementations it is a requirement to pass them the
highest power level which will enter a power down state during a PSCI
CPU_SUSPEND or SYSTEM_SUSPEND API invocation. This patch passes this power level
to the SPD in the "max_off_pwrlvl" parameter of the svc_suspend() hook.
Currently, the highest power level which was requested to be placed in a low
power state (retention or power down) is passed to the SPD svc_suspend_finish()
hook. This hook is called after emerging from the low power state. It is more
useful to pass the highest power level which was powered down instead. This
patch does this by changing the semantics of the parameter passed to an SPD's
svc_suspend_finish() hook. The name of the parameter has been changed from
"suspend_level" to "max_off_pwrlvl" as well. Same changes have been made to the
parameter passed to the tsp_cpu_resume_main() function.
NOTE: THIS PATCH CHANGES THE SEMANTICS OF THE EXISTING "svc_suspend_finish()"
API BETWEEN THE PSCI AND SPD/SP IMPLEMENTATIONS. THE LATTER MIGHT NEED
UPDATES TO ENSURE CORRECT BEHAVIOUR.
Change-Id: If3a9d39b13119bbb6281f508a91f78a2f46a8b90
Achin Gupta
committed
on 10 Sep 2015
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2015-09-02 |
Merge pull request #383 from vikramkanigiri/vk/tf-issues-314-v1
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Ensure BL2 security state is secure
danh-arm
committed
on 2 Sep 2015
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Ensure BL2 security state is secure
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BL2 loads secure runtime code(BL3-1, BL3-2) and hence it has to
run in secure world otherwise BL3-1/BL3-2 have to execute from
non-secure memory. Hence, This patch removes the change_security_state()
call in bl1_run_bl2() and replaces it with an assert to confirm
the BL2 as secure.
Fixes ARM-software/tf-issues#314
Change-Id: I611b83f5c4090e58a76a2e950b0d797b46df3c29
Vikram Kanigiri
committed
on 2 Sep 2015
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Merge pull request #382 from vikramkanigiri/vk/tf-issues-312
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Configure all secure interrupts on ARM platforms
danh-arm
committed
on 2 Sep 2015
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Merge pull request #381 from vikramkanigiri/hl/gic_v3
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Remove EL2/EL1 GICv3 register updates
danh-arm
committed
on 2 Sep 2015
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2015-09-01 |
Configure all secure interrupts on ARM platforms
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ARM TF configures all interrupts as non-secure except those which
are present in irq_sec_array. This patch updates the irq_sec_array
with the missing secure interrupts for ARM platforms.
It also updates the documentation to be inline with the latest
implementation.
Fixes ARM-software/tf-issues#312
Change-Id: I39956c56a319086e3929d1fa89030b4ec4b01fcc
Vikram Kanigiri
committed
on 1 Sep 2015
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Remove EL2/EL1 GICv3 register updates
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From Linux 3.17 onwards, the mainline kernel has support for GICv3
systems and if EL3 exists, it only needs to initialise ICC_SRE_EL3.SRE
and ICC_SRE_EL3.Enable to 1. Hence, this patch removes the redundant
updates of ICC_SRE_EL2 and ICC_PMR_EL1.
NOTE: For partner software's which enter kernel in EL1,
ICC_SRE_EL2.Enable and ICC_SRE_EL2.SRE bit needs to be set to 1
in EL2 before jumping to linux.
Change-Id: I09ed47869351b08a3b034735f532bc677eaa6917
Vikram Kanigiri
committed
on 1 Sep 2015
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Merge pull request #375 from vwadekar/clear-videomem-region-v2
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Tegra: fix logic to clear videomem regions
danh-arm
committed
on 1 Sep 2015
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2015-08-26 |
Tegra: fix logic to clear videomem regions
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The previous logic in the memctrl driver was not catering to cases
where the new memory region lied inside the older region. This patch
fixes the if/elseif/elseif logic in the driver to take care of this
case.
Reported by: Vikram Kanigiri <vikram.kanigiri@arm.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 26 Aug 2015
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2015-08-25 |
Merge pull request #371 from vwadekar/retention-entry-v3
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Retention entry v3
Achin Gupta
committed
on 25 Aug 2015
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2015-08-24 |
Tegra210: wait for 512 timer ticks before retention entry
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This patch programs the CPUECTLR_EL1 and L2ECTLR_EL1 registers,
so that the core waits for 512 generic timer CNTVALUEB ticks before
entering retention state, after executing a WFI instruction.
This functionality is configurable and can be enabled for platforms
by setting the newly defined 'ENABLE_L2_DYNAMIC_RETENTION' and
'ENABLE_CPU_DYNAMIC_RETENTION' flag.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 24 Aug 2015
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Add macros for retention control in Cortex-A53/A57
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This patch adds macros suitable for programming the Advanced
SIMD/Floating-point (only Cortex-A53), CPU and L2 dynamic
retention control policy in the CPUECTLR_EL1 and L2ECTLR
registers.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 24 Aug 2015
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2015-08-21 |
Merge pull request #368 from jcastillo-arm/jc/genfw/1126
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TBB: abort boot if BL3-2 cannot be authenticated
danh-arm
committed
on 21 Aug 2015
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2015-08-20 |
Merge pull request #367 from soby-mathew/sm/mig_guide_fix
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docs: Fixes to platform-migration-guide.md
danh-arm
committed
on 20 Aug 2015
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TBB: abort boot if BL3-2 cannot be authenticated
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BL3-2 image (Secure Payload) is optional. If the image cannot be
loaded a warning message is printed and the boot process continues.
According to the TBBR document, this behaviour should not apply in
case of an authentication error, where the boot process should be
aborted.
This patch modifies the load_auth_image() function to distinguish
between a load error and an authentication error. The caller uses
the return value to abort the boot process or continue.
In case of authentication error, the memory region used to store
the image is wiped clean.
Change-Id: I534391d526d514b2a85981c3dda00de67e0e7992
Juan Castillo
committed
on 20 Aug 2015
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2015-08-18 |
docs: Fixes to platform-migration-guide.md
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This patch corrects some typos in the platform migration guide. More
importantly, the commit ID of the patch that implements migration of ARM
Reference platforms to the new platform API has been corrected.
Change-Id: Ib0109ea42c3d2bad2c6856ab725862652da7f3c8
Soby Mathew
authored
on 18 Aug 2015
Achin Gupta
committed
on 18 Aug 2015
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Merge pull request #365 from mtk09422/plat_topology
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mt8173: Fix cluster 0 core count
danh-arm
committed
on 18 Aug 2015
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Merge pull request #364 from mtk09422/spm_suspend
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mt8173: update spm wake_src setting
danh-arm
committed
on 18 Aug 2015
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Merge pull request #362 from jcastillo-arm/jc/inline
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Fix build error with optimizations disabled (-O0)
danh-arm
committed
on 18 Aug 2015
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mt8173: Fix cluster 0 core count
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Use constant macro defined in platform_def.h to replace hardcoded value.
This patch fix following assert in new psci-1.0 framework.
ASSERT: populate_power_domain_tree <183> : j == PLATFORM_CORE_COUNT
Change-Id: I9b7eda525479464a8c3805b6fe14ffb10debaf72
Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Jimmy Huang
authored
on 14 Aug 2015
Yidi Lin
committed
on 18 Aug 2015
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mt8173: update spm wake_src setting
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1. SEJ should not be one of the wake up sources
BUG=chrome-os-partner:38426
TEST=powerd_dbus_suspend
Change-Id: If8f3f19a885e66d7c10b472c2e3182a5affa4773
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
kenny liang
authored
on 11 Aug 2015
Yidi Lin
committed
on 18 Aug 2015
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2015-08-17 |
Merge pull request #361 from achingupta/for_sm/psci_proto_v5
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For sm/psci proto v5
Achin Gupta
committed
on 17 Aug 2015
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2015-08-13 |
PSCI: Rework generic code to conform to coding guidelines
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This patch reworks the PSCI generic implementation to conform to ARM
Trusted Firmware coding guidelines as described here:
https://github.com/ARM-software/arm-trusted-firmware/wiki
This patch also reviews the use of signed data types within PSCI
Generic code and replaces them with their unsigned counterparts wherever
they are not appropriate. The PSCI_INVALID_DATA macro which was defined
to -1 is now replaced with PSCI_INVALID_PWR_LVL macro which is defined
to PLAT_MAX_PWR_LVL + 1.
Change-Id: Iaea422d0e46fc314e0b173c2b4c16e0d56b2515a
Soby Mathew
authored
on 29 Jul 2015
Achin Gupta
committed
on 13 Aug 2015
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PSCI: Add documentation and fix plat_is_my_cpu_primary()
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This patch adds the necessary documentation updates to porting_guide.md
for the changes in the platform interface mandated as a result of the new
PSCI Topology and power state management frameworks. It also adds a
new document `platform-migration-guide.md` to aid the migration of existing
platform ports to the new API.
The patch fixes the implementation and callers of
plat_is_my_cpu_primary() to use w0 as the return parameter as implied by
the function signature rather than x0 which was used previously.
Change-Id: Ic11e73019188c8ba2bd64c47e1729ff5acdcdd5b
Soby Mathew
authored
on 8 Jun 2015
Achin Gupta
committed
on 13 Aug 2015
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PSCI: Validate non secure entrypoint on ARM platforms
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This patch implements the platform power managment handler to verify
non secure entrypoint for ARM platforms. The handler ensures that the
entry point specified by the normal world during CPU_SUSPEND, CPU_ON
or SYSTEM_SUSPEND PSCI API is a valid address within the non secure
DRAM.
Change-Id: I4795452df99f67a24682b22f0e0967175c1de429
Soby Mathew
authored
on 15 Jul 2015
Achin Gupta
committed
on 13 Aug 2015
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