2015-01-26 |
Merge pull request #243 from soby-mathew/sm/psci_cleanup_1
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Clean-up PSCI code and introduce early validation of parameters v3
danh-arm
committed
on 26 Jan 2015
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2015-01-23 |
Return success if an interrupt is seen during PSCI CPU_SUSPEND
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This patch adds support to return SUCCESS if a pending interrupt is
detected during a CPU_SUSPEND call to a power down state. The check
is performed as late as possible without losing the ability to return
to the caller. This reduces the overhead incurred by a CPU in
undergoing a complete power cycle when a wakeup interrupt is already
pending.
Fixes ARM-Software/tf-issues#102
Change-Id: I1aff04a74b704a2f529734428030d1d10750fd4b
Soby Mathew
committed
on 23 Jan 2015
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Validate power_state and entrypoint when executing PSCI calls
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This patch allows the platform to validate the power_state and
entrypoint information from the normal world early on in PSCI
calls so that we can return the error safely. New optional
pm_ops hooks `validate_power_state` and `validate_ns_entrypoint`
are introduced to do this.
As a result of these changes, all the other pm_ops handlers except
the PSCI_ON handler are expected to be successful. Also, the PSCI
implementation will now assert if a PSCI API is invoked without the
corresponding pm_ops handler being registered by the platform.
NOTE : PLATFORM PORTS WILL BREAK ON MERGE OF THIS COMMIT. The
pm hooks have 2 additional optional callbacks and the return type
of the other hooks have changed.
Fixes ARM-Software/tf-issues#229
Change-Id: I036bc0cff2349187c7b8b687b9ee0620aa7e24dc
Soby Mathew
committed
on 23 Jan 2015
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Save 'power_state' early in PSCI CPU_SUSPEND call
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This patch adds support to save the "power state" parameter before the
affinity level specific handlers are called in a CPU_SUSPEND call.
This avoids the need to pass the power_state as a parameter to the
handlers and Secure Payload Dispatcher (SPD) suspend spd_pm_ops.
The power_state arguments in the spd_pm_ops operations are now reserved
and must not be used. The SPD can query the relevant power_state fields
by using the psci_get_suspend_afflvl() & psci_get_suspend_stateid() APIs.
NOTE: THIS PATCH WILL BREAK THE SPD_PM_OPS INTERFACE. HENCE THE SECURE
PAYLOAD DISPATCHERS WILL NEED TO BE REWORKED TO USE THE NEW INTERFACE.
Change-Id: I1293d7dc8cf29cfa6a086a009eee41bcbf2f238e
Soby Mathew
committed
on 23 Jan 2015
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Rework internal API to save non-secure entry point info
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This patch replaces the internal psci_save_ns_entry() API with a
psci_get_ns_ep_info() API. The new function splits the work done by the
previous one such that it populates and returns an 'entry_point_info_t'
structure with the information to enter the normal world upon completion
of the CPU_SUSPEND or CPU_ON call. This information is used to populate
the non-secure context structure separately.
This allows the new internal API `psci_get_ns_ep_info` to return error
and enable the code to return safely.
Change-Id: Ifd87430a4a3168eac0ebac712f59c93cbad1b231
Soby Mathew
committed
on 23 Jan 2015
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PSCI: Check early for invalid CPU state during CPU ON
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This patch moves the check for valid CPU state during
PSCI_CPU_ON to before the non secure entry point is programmed
so as to enable it to return early on error.
Change-Id: I1b1a21be421e2b2a6e33db236e91dee8688efffa
Soby Mathew
committed
on 23 Jan 2015
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Remove `ns_entrypoint` and `mpidr` from parameters in pm_ops
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This patch removes the non-secure entry point information being passed
to the platform pm_ops which is not needed. Also, it removes the `mpidr`
parameter for platform pm hooks which are meant to do power management
operations only on the current cpu.
NOTE: PLATFORM PORTS MUST BE UPDATED AFTER MERGING THIS COMMIT.
Change-Id: If632376a990b7f3b355f910e78771884bf6b12e7
Soby Mathew
committed
on 23 Jan 2015
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2015-01-22 |
Merge pull request #240 from danh-arm/sm/rem_coh_mem
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Remove coherent memory v2
danh-arm
committed
on 22 Jan 2015
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Remove coherent memory from the BL memory maps
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This patch extends the build option `USE_COHERENT_MEMORY` to
conditionally remove coherent memory from the memory maps of
all boot loader stages. The patch also adds necessary
documentation for coherent memory removal in firmware-design,
porting and user guides.
Fixes ARM-Software/tf-issues#106
Change-Id: I260e8768c6a5c2efc402f5804a80657d8ce38773
Soby Mathew
authored
on 8 Jan 2015
Dan Handley
committed
on 22 Jan 2015
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Move bakery algorithm implementation out of coherent memory
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This patch moves the bakery locks out of coherent memory to normal memory.
This implies that the lock information needs to be placed on a separate cache
line for each cpu. Hence the bakery_lock_info_t structure is allocated in the
per-cpu data so as to minimize memory wastage. A similar platform per-cpu
data is introduced for the platform locks.
As a result of the above changes, the bakery lock api is completely changed.
Earlier, a reference to the lock structure was passed to the lock implementation.
Now a unique-id (essentially an index into the per-cpu data array) and an offset
into the per-cpu data for bakery_info_t needs to be passed to the lock
implementation.
Change-Id: I1e76216277448713c6c98b4c2de4fb54198b39e0
Soby Mathew
authored
on 8 Jan 2015
Dan Handley
committed
on 22 Jan 2015
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Add macros for domain specific barriers.
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This patch adds helper macros for barrier operations that specify
the type of barrier (dmb, dsb) and the shareability domain (system,
inner-shareable) it affects.
Change-Id: I4bf95103e79da212c4fbdbc13d91ad8ac385d9f5
Soby Mathew
authored
on 30 Dec 2014
Dan Handley
committed
on 22 Jan 2015
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Remove the wfe() for bounded wait in bakery_lock
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This patch is an optimization in the bakery_lock_get() function
which removes the wfe() when waiting for other contenders to choose
their ticket i.e when their `entering` flag is set. Since the time
taken to execute bakery_get_ticket() by other contenders is bounded,
this wait is a bounded time wait. Hence the removal of wfe() and the
corresponding sev() and dsb() in bakery_get_ticket() may result
in better time performance during lock acquisition.
Change-Id: I141bb21294226b54cb6e89e7cac0175c553afd8d
Soby Mathew
authored
on 18 Nov 2014
Dan Handley
committed
on 22 Jan 2015
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2015-01-16 |
Merge pull request #235 from soby-mathew/sm/inv_cpu_ops
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Invalidate the dcache after initializing cpu-ops
danh-arm
committed
on 16 Jan 2015
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Merge pull request #233 from jcastillo-arm/jc/tf-issues/254
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Juno: Add support for image overlaying in Trusted SRAM
danh-arm
committed
on 16 Jan 2015
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2015-01-13 |
Invalidate the dcache after initializing cpu-ops
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This patch fixes a crash due to corruption of cpu_ops
data structure. During the secondary CPU boot, after the
cpu_ops has been initialized in the per cpu-data, the
dcache lines need to invalidated so that the update in
memory can be seen later on when the dcaches are turned ON.
Also, after initializing the psci per cpu data, the dcache
lines are flushed so that they are written back to memory
and dirty dcache lines are avoided.
Fixes ARM-Software/tf-issues#271
Change-Id: Ia90f55e9882690ead61226eea5a5a9146d35f313
Soby Mathew
committed
on 13 Jan 2015
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2015-01-12 |
Merge pull request #232 from jcastillo-arm/jc/fix_doc_bl31
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Fix reset to BL3-1 instructions in user guide, part 3
danh-arm
committed
on 12 Jan 2015
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Fix reset to BL3-1 instructions in user guide, part 3
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Patch 20d51ca moved the shared data page from the top of the
Trusted SRAM to the bottom, changing the load addresses of BL3-1
and BL3-2.
This patch updates BL3-1 and BL3-2 addresses in the instructions
to run the Trusted Firmware on FVP using BL3-1 as reset vector.
This patch is similar to but distinct from bfb1dd5 and 7ea4c43.
Change-Id: I6b467f9a82360a5e2181db99fea881487de52704
Juan Castillo
committed
on 12 Jan 2015
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Merge pull request #231 from jcastillo-arm/jc/fip_bin
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Specify FIP filename at build time
danh-arm
committed
on 12 Jan 2015
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Merge pull request #230 from sandrine-bailleux/sb/doc-updates
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User Guide: Enable secure memory on Foundation FVP
danh-arm
committed
on 12 Jan 2015
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Merge pull request #229 from sandrine-bailleux/sb/tf-issue-273
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Prevent optimisation of sysregs accessors calls
danh-arm
committed
on 12 Jan 2015
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Merge pull request #228 from jcastillo-arm/jc/tf-issues/274
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Bug fix: initialize bl30_image_info fields before use
danh-arm
committed
on 12 Jan 2015
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Juno: Add support for image overlaying in Trusted SRAM
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This patch allows the BL3-1 NOBITS section to overlap the BL1 R/W
section since the former will always be used after the latter.
Similarly, the BL3-2 NOBITS section can overlay the BL2 image
when BL3-2 is loaded in Trusted SRAM.
Due to the current size of the images, there is no actual overlap.
Nevertheless, this reorganization may help to optimise the Trusted
SRAM usage when the images size grows.
Note that because BL3-1 NOBITS section is allowed to overlap the
BL1 R/W section, BL1 global variables will remain valid only until
execution reaches the BL3-1 entry point during a cold boot.
Documentation updated accordingly.
Fixes ARM-software/tf-issues#254
Change-Id: Id538f4d1c7f1f7858108280fd7b97e138572b879
Juan Castillo
committed
on 12 Jan 2015
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2015-01-09 |
User Guide: Enable secure memory on Foundation FVP
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Previously, the User Guide recommended launching the Foundation
FVP with the parameter --no-secure-memory, which disabled security
control of the address map. This was due to missing support for
secure memory regions in v1 of the Foundation FVP. This is no longer
needed as secure memory is now supported on the Foundation FVP.
This patch updates the User Guide to recommend enabling secure
memory instead.
Change-Id: Ifae53c10ff6e1c7c6724af20e05a3d3a88f6a5ad
Sandrine Bailleux
committed
on 9 Jan 2015
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2015-01-08 |
Bug fix: initialize bl30_image_info fields before use
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This patch initializes the version field in the bl30_image_info
structure when loading BL30. This initialization must be done before
calling load_image().
Fixes ARM-software/tf-issues#274
Change-Id: I74a05167d66fff51d257ad611abc7b5436e5d912
Juan Castillo
committed
on 8 Jan 2015
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2015-01-07 |
Merge pull request #222 from jbech-linaro/user_guide_toc_links
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Create TOC links in the User Guide markdown file
danh-arm
committed
on 7 Jan 2015
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Prevent optimisation of sysregs accessors calls
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Calls to system register read accessors functions may be optimised
out by the compiler if called twice in a row for the same register.
This is because the compiler is not aware that the result from
the instruction may be modified by external agents. Therefore, if
nothing modifies the register between the 2 reads as far as the
compiler knows then it might consider that it is useless to read
it twice and emit only 1 call.
This behaviour is faulty for registers that may not have the same
value if read twice in succession. E.g.: counters, timer
control/countdown registers, GICv3 interrupt status registers and
so on.
The same problem happens for calls to system register write
accessors functions. The compiler might optimise out some calls
if it considers that it will produce the same result. Again, this
behaviour is faulty for cases where intermediate writes to these
registers make a difference in the system.
This patch fixes the problem by making these assembly register
accesses volatile.
Fixes ARM-software/tf-issues#273
Change-Id: I33903bc4cc4eea8a8d87bc2c757909fbb0138925
Sandrine Bailleux
committed
on 7 Jan 2015
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Create Table of Content links in markdown files
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Fixes arm-software/tf-issues#276
Joakim Bech
committed
on 7 Jan 2015
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Merge pull request #226 from sandrine-bailleux/sb/tf-issues-279
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fip_create: don't succeed if one of the passed files doesn't exist
danh-arm
committed
on 7 Jan 2015
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Merge pull request #227 from soby-mathew/sm/afflvl_fix
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Fix CPU_SUSPEND when invoked with affinity level higher than get_max_aff...
danh-arm
committed
on 7 Jan 2015
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Merge pull request #225 from sandrine-bailleux/sb/remove-IRQ_SEC_SGI_8
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Remove IRQ_SEC_SGI_8 constant
danh-arm
committed
on 7 Jan 2015
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