LuminaSensum/arm-trusted-firmware

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LuminaSensum / arm-trusted-firmware

2018-02-12	Unverified 15e5958 Browse files » Merge pull request #1256 from jeenu-arm/tsp-ehf ... TSP changes for EHF davidcunado-arm authored on 12 Feb 2018 GitHub committed on 12 Feb 2018
2018-02-09	53a98be Browse files » qemu: Fix interrupt type check ... Function plat_ic_get_pending_interrupt_type() should return interrupt type, not id. The function is used in aarch64 exception handling and currently the irq/fiq forwarding fails if a secure interrupt happens while running normal world. The qemu-specific gic file does not contain any extra functionality so it can be removed and common file can be used instead. fixes arm-software/tf-issues#546 Signed-off-by: Santeri Salko <santeri.salko@gmail.com> Santeri Salko committed on 9 Feb 2018
2018-02-08	Unverified e47a832 Browse files » Merge pull request #1257 from vchong/poplar_maintainer ... maintainers.rst: Add maintainer for plat Poplar davidcunado-arm authored on 8 Feb 2018 GitHub committed on 8 Feb 2018
	Unverified 976f7f4 Browse files » Merge pull request #1251 from vchong/ld_img_v2 ... poplar: misc updates davidcunado-arm authored on 8 Feb 2018 GitHub committed on 8 Feb 2018
	Unverified 014334c Browse files » Merge pull request #1260 from sandrine-bailleux-arm/topics/sb/fix-zlib-build ... zlib: Fix build error when LOG_LEVEL=50 davidcunado-arm authored on 8 Feb 2018 GitHub committed on 8 Feb 2018
	5754607 Browse files » zlib: Fix build error when LOG_LEVEL=50 ... When enabling VERBOSE() traces, the zlib library fails to compile because of an incompatible format specifier string. Fix that. Change-Id: I74ff1c8dc2e6157ee982f7754bce4504599e3013 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Sandrine Bailleux committed on 8 Feb 2018
	Unverified cc40f7f Browse files » Merge pull request #1254 from masahir0y/bl2-at-el3 ... Fix zero_normalmem() for BL2_AT_EL3 davidcunado-arm authored on 8 Feb 2018 GitHub committed on 8 Feb 2018
2018-02-07	5c0bda7 Browse files » optee: print header info before validate ... Currently optee header info is only printed after it is validated, but this does not help with debugging in case of error, so print it before. Signed-off-by: Victor Chong <victor.chong@linaro.org> Victor Chong committed on 7 Feb 2018
	3b12a6f Browse files » hikey*, poplar: platform.mk: Fix typo in variable assignments ... Signed-off-by: Victor Chong <victor.chong@linaro.org> Victor Chong committed on 7 Feb 2018
	f3d522b Browse files » poplar: Support Trusted OS extra image (OP-TEE header) parsing ... Signed-off-by: Victor Chong <victor.chong@linaro.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Victor Chong committed on 7 Feb 2018
	0d8052a Browse files » poplar: Add LOAD_IMAGE_V2 support ... Signed-off-by: Victor Chong <victor.chong@linaro.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Victor Chong committed on 7 Feb 2018
	8ad132b Browse files » poplar: Add build option for dram size ... Signed-off-by: Victor Chong <victor.chong@linaro.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Victor Chong committed on 7 Feb 2018
	ce2547f Browse files » poplar: Fix typo ... Signed-off-by: Victor Chong <victor.chong@linaro.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Victor Chong committed on 7 Feb 2018
	b715f11 Browse files » poplar: Remove unused function prototype ... Signed-off-by: Victor Chong <victor.chong@linaro.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Victor Chong committed on 7 Feb 2018
	db04653 Browse files » maintainers.rst: Add maintainer for plat Poplar ... Signed-off-by: Victor Chong <victor.chong@linaro.org> Victor Chong committed on 7 Feb 2018
2018-02-06	Unverified 5b75b4a Browse files » Merge pull request #1173 from etienne-lms/armv7-qemu ... support to boot OP-TEE on AArch32/Armv7+example with Cortex-A15/Qemu davidcunado-arm authored on 6 Feb 2018 GitHub committed on 6 Feb 2018
	95ae5b0 Browse files » [fix] aarch32: optee: define the OP-TEE secure payload ... As per MISRA C-2012 Rule 10.4. arg0 is a u_register_t, can be a 32bit or 64bit upon architecture. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Etienne Carriere committed on 6 Feb 2018
	fb750ee Browse files » interrupt-framework-design.rst: Cosmetic changes ... Change-Id: Id2e2800af59ca35fc0c4cfdddd9f5c5afd56a4db Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> Jeenu Viswambharan committed on 6 Feb 2018
	6027796 Browse files » TSPD: Require NS preemption along with EL3 exception handling ... At present, the build option TSP_NS_INTR_ASYNC_PREEMPT controls how Non-secure interrupt affects TSPs execution. When TSP is executing: 1. When TSP_NS_INTR_ASYNC_PREEMPT=0, Non-secure interrupts are received at the TSP's exception vector, and TSP voluntarily preempts itself. 2. When TSP_NS_INTR_ASYNC_PREEMPT=1, Non-secure interrupts causes a trap to EL3, which preempts TSP execution. When EL3 exception handling is in place (i.e., EL3_EXCEPTION_HANDLING=1), FIQs are always trapped to EL3. On a system with GICv3, pending NS interrupts while TSP is executing will be signalled as FIQ (which traps to EL3). This situation necessitates the same treatment applied to case (2) above. Therefore, when EL3 exception handling is in place, additionally require that TSP_NS_INTR_ASYNC_PREEMPT is set to one 1. Strictly speaking, this is not required on a system with GICv2, but the same model is uniformly followed regardless, for simplicity. Relevant documentation updated. Change-Id: I928a8ed081fb0ac96e8b1dfe9375c98384da1ccd Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> Jeenu Viswambharan committed on 6 Feb 2018
	1dd022c Browse files » TSPD: Explicitly allow NS preemption for Yielding SMCs ... When EL3 exception handling is in effect (i.e., EL3_EXCEPTION_HANDLING=1), Non-secure interrupts can't preempt Secure execution. However, for yielding SMCs, preemption by Non-secure interupts is intended. This patch therefore adds a call to ehf_allow_ns_preemption() before dispatching a Yielding SMC to TSP. Change-Id: Ia3a1ae252f3adc0f14e6d7e0502f251bdb349bdf Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> Jeenu Viswambharan committed on 6 Feb 2018
	26ea390 Browse files » Deprecate one EL3 interrupt routing model with EL3 exception handling ... When ARM Trusted Firmware is built with EL3_EXCEPTION_HANDLING=1, EL3 interrupts (INTR_TYPE_EL3) will always preempt both Non-secure and secure execution. The interrupt management framework currently treats EL3 interrupt routing as valid. For the above reason, this patch makes them invalid when EL3_EXCEPTION_HANDLING is in effect. Change-Id: I95bca8f5dc8df8eb0ff6f305cfba098611522a39 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> Jeenu Viswambharan committed on 6 Feb 2018
	c8b55b8 Browse files » Add EL3_EXCEPTION_HANDLING to build command line ... Commit `21b818c` (BL31: Introduce Exception Handling Framework) introduced the build option EL3_EXCEPTION_HANDLING, but missed to pass that to the build command line. This patch fixes that. Change-Id: I0a1be2c7b41a81e748ad7d6cf795aab7f6d19193 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> Jeenu Viswambharan committed on 6 Feb 2018
	Unverified 9fd2f13 Browse files » Merge pull request #1224 from masahir0y/gzip ... Support GZIP-compressed images for faster loading and verification davidcunado-arm authored on 6 Feb 2018 GitHub committed on 6 Feb 2018
2018-02-05	765ed9f Browse files » qemu: support ARMv7/Cortex-A15 ... Define Qemu AArch32 implementation for some platform functions (core position, secondary boot cores, crash console). These are derived from the AArch64 implementation. BL31 on Qemu is needed only for ARMv8 and later. On ARMv7, BL32 is the first executable image after BL2. Support SP_MIN and OP-TEE as BL32: create a sp_min make script target in Qemu, define mapping for IMAGE_BL32 Minor fix Qemu return value type for plat_get_ns_image_entrypoint(). Qemu model for the Cortex-A15 does not support the virtualization extension although the core expects it. To overcome the issue, Qemu ARMv7 configuration set ARCH_SUPPORTS_VIRTUALIZATION to 0. Add missing AArch32 assembly macro arm_print_gic_regs from ARM platform used by the Qemu platform. Qemu Cortex-A15 model integrates a single cluster with up to 4 cores. Change-Id: I65b44399071d6f5aa40d5183be11422b9ee9ca15 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Etienne Carriere committed on 5 Feb 2018
2018-02-05	10c6695 Browse files » aarch32: optee: define the OP-TEE secure payload ... AArch32 only platforms can boot the OP-TEE secure firmware as a BL32 secure payload. Such configuration can be defined through AARCH32_SP=optee. The source files can rely on AARCH32_SP_OPTEE to condition OP-TEE boot specific instruction sequences. OP-TEE does not expect ARM Trusted Firmware formatted structure as boot argument. Load sequence is expected to have already loaded to OP-TEE boot arguments into the bl32 entrypoint info structure. Last, AArch32 platform can only boot AArch32 OP-TEE images. Change-Id: Ic28eec5004315fc9111051add6bb1a1d607fc815 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Etienne Carriere committed on 5 Feb 2018
2018-02-02	Unverified 10787b0 Browse files » Merge pull request #1249 from masahir0y/uniphier ... uniphier: fix and improve memory layout davidcunado-arm authored on 2 Feb 2018 GitHub committed on 2 Feb 2018
	3fe81dc Browse files » aarch32: use lr as bl32 boot argument on aarch32 only systems ... Add 'lr_svc' as a boot parameter in AArch32 bl1. This is used by Optee and Trusty to get the non-secure entry point on AArch32 platforms. This change is not ported in AArch64 mode where the BL31, not BL32, is in charge of booting the non secure image (BL33). Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Etienne Carriere committed on 2 Feb 2018
	Unverified 9c00555 Browse files » Merge pull request #1253 from dp-arm/dp/amu32 ... AMUv1 support for AArch32 davidcunado-arm authored on 2 Feb 2018 GitHub committed on 2 Feb 2018
	4f557c7 Browse files » uniphier: add ULL to physical address literals ... Looks like this is requirement in the pre-merge static analysis. misra_violation: [Required] MISRA C-2012 Rule 7.2 violation: Unsigned constants must be declared with U or u suffix. Adding ULL as requested. I used ULL() macros for BL*_{BASE,LIMIT} because they are referenced from linker scripts. Requested-by: David Cunado <david.cunado@arm.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Masahiro Yamada committed on 2 Feb 2018
	9c740a5 Browse files » uniphier: allocate xlat region of on-chip SRAM only when needed ... Currently, the xlat region of the on-chip SRAM is always allocated for all BL images. The access to the on-chip SRAM is necessary for loading images from a USB memory device (i.e. when updating firmware), so unneeded for the usual boot procedure. To avoid this waste, allocate the xlat region dynamically only for BL2, and only when it is necessary. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Masahiro Yamada committed on 2 Feb 2018