Set NS version SCTLR during warmboot path ...

When ARM TF executes in AArch32 state, the NS version of SCTLR
is not being set during warmboot flow. This results in secondary
CPUs entering the Non-secure world with the default reset value
in SCTLR.

This patch explicitly sets the value of the NS version of SCTLR
during the warmboot flow rather than relying on the h/w.

Change-Id: I86bf52b6294baae0a5bd8af0cd0358cc4f55c416
Signed-off-by: David Cunado <david.cunado@arm.com>

Merge pull request #1083 from soby-mathew/sm/fix_optee_map ...

Fix BL2 memory map when OP-TEE is the Secure Payload

Fix BL2 memory map when OP-TEE is the Secure Payload ...

The commit 3eb2d67 optimizes the memory map for BL2 when TSP
is not present. But this also broke OP-TEE as it was reusing
the TSP mapping. This patch fixes this problem by adding a
separate mapping for OP-TEE in the BL2 memory map table.

Change-Id: I130a2ea552b7b62d8478081feb1f4ddf5292a118
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

Merge pull request #1081 from masahir0y/uniphier ...

uniphier: fix-up for PXs3 SoC

uniphier: work around Boot ROM bug for USB boot mode of PXs3 SoC ...

Due to a bug in the Boot ROM, the USB load API turned out not working
as expected.  It is unfixable because the Boot ROM is hard-wired.

Add work around code in TF to bypass the problematic Boot ROM code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

uniphier: fix code indent for conditional statement ...

checkpatch.pl from Linux reports tons of coding style errors and
warnings.  I am just fixing under plat/socionext/uniphier/.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Merge pull request #1072 from sandrine-bailleux-arm/sb/tsp-mapping ...

ARM platforms: Map TSP only when TSPD is included

ARM platforms: Map TSP only when TSPD is included ...

This patch ensures that the ARM_MAP_TSP_SEC_MEM memory region is mapped
in BL2 only if the TSPD has been included in the build. This saves one
entry in the plat_arm_mmap[] array and avoids to map extra memory when
it's not needed.

Change-Id: I6ae60822ff8f0de198145925b0b0d45355179a94
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Merge pull request #1079 from douglas-raillard-arm/dr/doc_fix_typo ...

porting-guide.rst: Fix some sections' level

Merge pull request #1077 from soby-mathew/sm/fix_juno_assert_lvl ...

Juno: Define PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO

porting-guide.rst: Fix some sections' level ...

Fix the level of the section
"13.   Function : plat_setup_psci_ops() [mandatory]",
including all the subsections.

Fix the level of the section
"12.7.   plat_psci_ops.pwr_domain_suspend_pwrdown_early() [optional]"
to lower it like the surrounding functions.

Change-Id: I781823bc96ece669f8fde4bd39c4e333c7bf4d1a
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>

Juno: Define PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO ...

This patch fixes the PLAT_LOG_LEVEL_ASSERT to 40 which corresponds
to LOG_LEVEL_INFO. Having this level of log for assertions means that the
`assert()` will not generate the strings implied in the expression taken
as parameter. This allows to save some memory when Juno is built for
LOG_LEVEL = LOG_LEVEL_VERBOSE and DEBUG = 1.

Fixes ARM-software/tf-issues#511

Change-Id: Id84a40f803ab07a5a8f6e587167af96694a07d04
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

Merge pull request #1069 from Leo-Yan/hikey_enable_watchdog_reset ...

Hikey: enable watchdog reset

Merge pull request #1074 from EvanLloyd/ejll/62_file_mode ...

fiptool: Update file open modes with 'b' (for Windows)

Merge pull request #1075 from robertovargas-arm/fix_el3_payload ...

Don't use zero_normalmem in bl2_platform_setup

Don't use zero_normalmem in bl2_platform_setup ...

zero_normalmem only can zero memory when caches are enabled
and the target memory is a normal memory, otherwise an abort is
generated. In the case of EL3_PAYLOAD_BASE bl2_platform_setup was
calling zero_normalmem with device memory and it generated an abort.

Change-Id: If013603f209a12af488a9c54481f97a8f395b26a
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

fiptool: Update file open modes with 'b' (for Windows) ...

Unix does not distinguish binary and text modes.
On Windows the 'b' flag (e.g. "rb" instead of "r") is used to
indicate that files should be opened in binary mode.
This has no impact on Unix, but is needed on Windows to avoid
end-of-line issues.

Change-Id: I69424c55735d5d563d36c50bedd6357b8e05137e
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>

Merge pull request #1073 from davidcunado-arm/dc/update_docs ...

Add usage note for FVP model versions 11.0 and 8.5

Merge pull request #1066 from islmit01/im/enable_cnp_bit ...

Enable CnP bit for ARMv8.2 CPUs

Merge pull request #1062 from jeenu-arm/cpu-fixes ...

Cpu macro fixes

Add usage note for FVP model versions 11.0 and 8.5 ...

The internal synchronisation timings of the FVP model version
11.0 build 11.0.34 and version 8.5 build 0.8.5202 has been
changed compared to older version of the models.

This change may have an impact on how the model behaves depending
on the workload being run on the model. For example test failures
have been seen where the primary core has powered on a secondary
core but was then starved of host CPU time and so was not able to
update power status, resulting a test failure due to an incorrect
status. This, or similar behaviour, is not to be expected from
real hardware platforms.

This patch adds a usage note on how to launch these models so
that internal synchronisation timing matches that of the older
version of the models, specifically adding the -Q 100 option.

Change-Id: If922afddba1581b7246ec889b3f1598533ea1b7e
Signed-off-by: David Cunado <david.cunado@arm.com>

Merge pull request #1071 from jeenu-arm/syntax-fix ...

plat/arm: Fix ARM_INSTANTIATE_LOCK syntax anomaly

Tegra: Rename CORTEX_A57_ACTLR_EL1 to *CPUACTLR* ...

CORTEX_A57_ACTLR_EL1 macro refers to the CPUACTLR_EL1 register. Since
ACTLR_EL1 is a different register (not implemented in Cortex-A57) this
patch renames this macro for clarity.

Change-Id: I94d7d564cd2423ae032bbdd59a99d2dc535cdff6
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>

HiKey: Rename CPUACTRL reg constants ...

Constants named as *ACTLR* refer in fact to the CPUACTRL_EL1 register.
Since ACTLR and ACTRL_EL1 are different registers this patch renames
these constants for clarity.

Change-Id: I2a9e402dab7b0fcb6e481ee0d8a11eda943ed299
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>

CPU: Correct names of implementation-defined aux regs ...

At present, various CPU register macros that refer to CPUACTLR are named
ACTLR. This patch fixes that.

The previous register names are retained, but guarded by the
ERROR_DEPRECATED macro, so as not to break platforms that continue using
the old names.

Change-Id: Ia872196d81803f8f390b887d149e0fd054df519b
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>

CPU: Make shifted constants unsigned ...

In order to avoid Undefined behavior, left operand in left-shift
expressions needs to be unsigned, and of sufficient size. The safest and
most consistent approach is to use unsigned long long type.

Change-Id: I9612f16a6e6ea4c7df62a02497d862abf19b8e1b
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>

plat/arm: Fix ARM_INSTANTIATE_LOCK syntax anomaly ...

The current definition of ARM_INSTANTIATE_LOCK macro includes a
semicolon, which means it's omitted where it's used. This is anomalous
for a C statement in global scope.

Fix this by removing semicolon from the definition; and where it's a
NOP, declare a file-scoped variable explicitly tagged as unused to avoid
compiler warning.

No functional changes.

Change-Id: I2c1d92ece4777e272a025011e03b8003f3543335
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

Merge pull request #1070 from rockchip-linux/rk3399-fixes-logic ...

rockchip/rk3399: Support Turning off VD_LOGIC during suspend-to-ram

Merge pull request #1068 from jenswi-linaro/optee_arm_plat ...

Optee arm platform common

Merge pull request #1056 from geesun/qx/interrupt-diags ...

update the interrupt diagrams