DSU erratum 936184 workaround ...

If the system is in near idle conditions, this erratum could cause a
deadlock or data corruption. This patch applies the workaround that
prevents this.

This DSU erratum affects only the DSUs that contain the ACP interface
and it was fixed in r2p0. The workaround is applied only to the DSUs
that are actually affected.

Link to respective Arm documentation:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.epm138168/index.html

Change-Id: I033213b3077685130fc1e3f4f79c4d15d7483ec9
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

Merge pull request #1516 from antonio-nino-diaz-arm/an/printf ...

Replace stdio.h functions by TF functions

Merge pull request #1502 from dp-arm/dp/irc ...

readme: Add information about the TF-A IRC channel

Merge pull request #1520 from robertovargas-arm/cci-dsb ...

cci: Use dsb to wait before reading status register

cci: Use dsb to wait before reading status register ...

The CCI500 TRM explicitily requires completion of the write
operation before the read operation, and it is not guaranteed
by dmb but it is dsb.

Change-Id: Ieeaa0d1a4b8fcb87108dea9b6de03d9c8a150829
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

Merge pull request #1510 from robertovargas-arm/romlib ...

Add support for moving libraries to ROM

Merge pull request #1519 from antonio-nino-diaz-arm/an/xlat-el2 ...

xlat v2: Support EL2 translation regime

Merge pull request #1518 from antonio-nino-diaz-arm/an/fix_mmc ...

mmc: Fix warning about usage of uninitialized variable

drivers/mmc: Fix warning about usage of uninitialized variable ...

Because of -Werror, this causes a build error.

Change-Id: I37a8c4bbfe3f2ced5e17981a2814985919ad483b
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

layerscape: stm32mp1: Migrate to enable_mmu_svc_mon() ...

Change-Id: I3d16b247a0fa457e6293e2d2c4503dfde1e51c1d
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

plat/arm: Migrate to enable_mmu_svc_mon() ...

Change-Id: I1bb310e1b05968d30b28913c4011c0601e1ae64e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

xlat v2: Support the EL2 translation regime ...

The translation library is useful elsewhere. Even though this repository
doesn't exercise the EL2 support of the library, it is better to have it
here as well to make it easier to maintain.

enable_mmu_secure() and enable_mmu_direct() have been deprecated. The
functions are still present, but they are behind ERROR_DEPRECATED and
they call the new functions enable_mmu_svc_mon() and
enable_mmu_direct_svc_mon().

Change-Id: I13ad10cd048d9cc2d55e0fff9a5133671b67dcba
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Merge pull request #1504 from hzhuang1/migrate_mmc ...

Migrate mmc

doc/maintainers: remove emmc framework ...

Remove emmc framework from maintain list.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

drivers/emmc: remove emmc framework ...

Replace emmc framework by mmc framework.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

plat/poplar: migrate to mmc framework ...

Migrate from emmc framework to mmc framework.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

plat/hikey: migrate to mmc framework ...

Migrate to mmc framework.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

drivers/dw_mmc: migrate to mmc framework ...

Migrate dw_mmc driver from emmc framework to mmc framework. The
emmc framework will be abandoned.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

drivers/mmc: set buswidth and speed before reading data ...

It should set buswidth and speed of mmc controller before accessing
mmc.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

drivers/mmc: make mmc_ext_csd aligned with 16 char ...

DMA is always used in mmc driver. So the buffer address should
always follow the DMA limitation.

There're same requirement in mmc_read_blocks()/mmc_write_blocks()
on parameter buf. Since parameter buf comes from io_block driver,
it's already handled in io_block driver.

At here, just make the minimum address alignment on 16 chars.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

drivers/mmc: fix lba param to int ...

mmc_read_blocks()/mmc_write_blocks() derived from io_block_ops_t
type. It means that lba param should be integer type, not
unsigned integer type.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

drivers/mmc: send CMD8 only for SD card in initialization ...

Sending CMD8 before CMD1 just causes to fetch data failure in eMMC.
Check whether it's eMMC first. If it's eMMC, send CMD1 command instead.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

Merge pull request #1505 from Yann-lms/mmc_delays ...

mmc: add required delays when retrying commands

Replace stdio.h functions by TF functions ...

Functions provided by stdio.h such as printf and sprintf are available
in the codebase, but they add a lot of code to the final image if they
are used:

- AArch64: ~4KB
- AArch32: ~2KB in T32, ~3KB in A32

tf_printf and tf_snprintf are a lot more simple, but it is preferable
to use them when possible because they are also used in common code.

Change-Id: Id09fd2b486198fe3d79276e2c27931595b7ba60e
Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

tf_snprintf: Add support for '%s' ...

Change-Id: Ia3a159444e638f63de7dc5a6a4b76169c757188a
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Merge pull request #1513 from antonio-nino-diaz-arm/an/xlat-caches ...

xlat v2: Cleanup and dcache coherency bug fix

xlat v2: Flush xlat tables after being modified ...

During cold boot, the initial translation tables are created with data
caches disabled, so all modifications go to memory directly. After the
MMU is enabled and data cache is enabled, any modification to the tables
goes to data cache, and eventually may get flushed to memory.

If CPU0 modifies the tables while CPU1 is off, CPU0 will have the
modified tables in its data cache. When CPU1 is powered on, the MMU is
enabled, then it enables coherency, and then it enables the data cache.
Until this is done, CPU1 isn't in coherency, and the translation tables
it sees can be outdated if CPU0 still has some modified entries in its
data cache.

This can be a problem in some cases. For example, the warm boot code
uses only the tables mapped during cold boot, which don't normally
change. However, if they are modified (and a RO page is made RW, or a XN
page is made executable) the CPU will see the old attributes and crash
when it tries to access it.

This doesn't happen in systems with HW_ASSISTED_COHERENCY or
WARMBOOT_ENABLE_DCACHE_EARLY. In these systems, the data cache is
enabled at the same time as the MMU. As soon as this happens, the CPU is
in coherency.

There was an attempt of a fix in psci_helpers.S, but it didn't solve the
problem. That code has been deleted. The code was introduced in commit
<264410306381> ("Invalidate TLB entries during warm boot").

Now, during a map or unmap operation, the memory associated to each
modified table is flushed. Traversing a table will also flush it's
memory, as there is no way to tell in the current implementation if the
table that has been traversed has also been modified.

Change-Id: I4b520bca27502f1018878061bc5fb82af740bb92
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Merge pull request #1501 from robertovargas-arm/cci ...

cci: Wait before reading status register

Add librom support in FVP ...

Change-Id: Idb9ba3864d6de3053260724f07172fd32c1523e0
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

Merge pull request #1512 from npoushin/integration ...

Add support for Arm System Guidance for Mobile fixed virtual platform