2015-06-17 |
Add a simple delay timer driver API
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The API is simple. The BSP or specific timer driver creates an
instance of timer_ops_t, fills in the timer specific data, then calls
timer_init(). The timer specific data includes a function pointer
to return the timer value and a clock multiplier/divider. The ratio
of the multiplier and the divider is the clock frequency in MHz.
After that, mdelay() or udelay() can be called to delay execution for
the specified time (milliseconds or microseconds, respectively).
Change-Id: Icf8a295e1d25874f789bf28b7412156329dc975c
Co-authored-by: Dan Handley <dan.handley@arm.com>
Ryan Harkin
authored
on 17 Mar 2015
Dan Handley
committed
on 17 Jun 2015
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2015-06-02 |
Merge pull request #305 from achingupta/ag/tf-issues#306
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Ag/tf issues#306
Achin Gupta
committed
on 2 Jun 2015
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Merge pull request #307 from soby-mathew/sm/css_bit_width_fix
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CSS: Extract primary cpu id using the correct bit width
Achin Gupta
committed
on 2 Jun 2015
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2015-05-29 |
Driver for 16550 UART interface
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This patch adds driver for the 16550 UART interface. The driver is exposed
as a console, which platforms can use to dump their boot/crash logs.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 29 May 2015
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2015-05-27 |
CSS: Extract primary cpu id using the correct bit width
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This patch fixes the incorrect bit width used to extract the primary
cpu id from `ap_data` exported by scp at SCP_BOOT_CFG_ADDR in
platform_is_primary_cpu().
Change-Id: I14abb361685f31164ecce0755fc1a145903b27aa
Soby Mathew
committed
on 27 May 2015
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2015-05-19 |
Fix reporting of interrupt ID in ARM GIC driver
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The ARM GIC driver treats the entire contents of the GICC_HPPIR as the interrupt
ID instead of just bits[9:0]. This could result in an SGI being treated as a
Group 1 interrupt on a GICv2 system.
This patch introduces a mask to retrieve only the ID from a read of GICC_HPPIR,
GICC_IAR and similar registers. The value read from these registers is masked
with this constant prior to use as an interrupt ID.
Fixes ARM-software/tf-issues#306
Change-Id: Ie3885157de33b71df9781a41f6ef015a30c4608d
Achin Gupta
committed
on 19 May 2015
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2015-04-28 |
Migrate FVP port to use common code
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Major update to the FVP platform port to use the common platform code
in (include/)plat/arm/* and (include/)plat/common/*. This mainly
consists of removing duplicated code but also introduces some small
behavioural changes where there was unnecessary variation between the
FVP and Juno ports. See earlier commit titled `Add common ARM and CSS
platform code` for details.
Also add support for Foundation FVP version 9.1 during FVP config
setup to prevent a warning being emitted in the console.
Change-Id: I254ca854987642ce09d1b924c9fd410a6e13e3bc
Dan Handley
committed
on 28 Apr 2015
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Add common ARM and CSS platform code
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This major change pulls out the common functionality from the
FVP and Juno platform ports into the following categories:
* (include/)plat/common. Common platform porting functionality that
typically may be used by all platforms.
* (include/)plat/arm/common. Common platform porting functionality
that may be used by all ARM standard platforms. This includes all
ARM development platforms like FVP and Juno but may also include
non-ARM-owned platforms.
* (include/)plat/arm/board/common. Common platform porting
functionality for ARM development platforms at the board
(off SoC) level.
* (include/)plat/arm/css/common. Common platform porting
functionality at the ARM Compute SubSystem (CSS) level. Juno
is an example of a CSS-based platform.
* (include/)plat/arm/soc/common. Common platform porting
functionality at the ARM SoC level, which is not already defined
at the ARM CSS level.
No guarantees are made about the backward compatibility of
functionality provided in (include/)plat/arm.
Also remove any unnecessary variation between the ARM development
platform ports, including:
* Unify the way BL2 passes `bl31_params_t` to BL3-1. Use the
Juno implementation, which copies the information from BL2 memory
instead of expecting it to persist in shared memory.
* Unify the TZC configuration. There is no need to add a region
for SCP in Juno; it's enough to simply not allow any access to
this reserved region. Also set region 0 to provide no access by
default instead of assuming this is the case.
* Unify the number of memory map regions required for ARM
development platforms, although the actual ranges mapped for each
platform may be different. For the FVP port, this reduces the
mapped peripheral address space.
These latter changes will only be observed when the platform ports
are migrated to use the new common platform code in subsequent
patches.
Change-Id: Id9c269dd3dc6e74533d0e5116fdd826d53946dc8
Dan Handley
committed
on 28 Apr 2015
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Add linker symbol declarations to bl_common.h
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Add extern declarations of linker symbols to bl_common.h. These are
used by platform ports to determine the memory layout of BL images.
Adding the declarations to this file facilitates removal of these
declarations from the platform porting source files in subsequent
patches.
Also remove the linker symbol declarations from common TSP source
code.
Change-Id: I8ed0426bc815317c4536b588e4e78bc15b4fe91c
Dan Handley
committed
on 28 Apr 2015
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2015-04-27 |
Add header guards to asm macro files
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Some assembly files containing macros are included like header files
into other assembly files. This will cause assembler errors if they
are included multiple times.
Add header guards to assembly macro files to avoid assembler errors.
Change-Id: Ia632e767ed7df7bf507b294982b8d730a6f8fe69
Dan Handley
committed
on 27 Apr 2015
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Remove use of PLATFORM_CACHE_LINE_SIZE
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The required platform constant PLATFORM_CACHE_LINE_SIZE is
unnecessary since CACHE_WRITEBACK_GRANULE effectively provides the
same information. CACHE_WRITEBACK_GRANULE is preferred since this
is an architecturally defined term and allows comparison with the
corresponding hardware register value.
Replace all usage of PLATFORM_CACHE_LINE_SIZE with
CACHE_WRITEBACK_GRANULE.
Also, add a runtime assert in BL1 to check that the provided
CACHE_WRITEBACK_GRANULE matches the value provided in CTR_EL0.
Change-Id: If87286be78068424217b9f3689be358356500dcd
Dan Handley
committed
on 27 Apr 2015
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Add TZC function to configure region 0
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Region 0 is special in TZC-400. It is possible to set the access
permissions for this but not the address range or filters to which
the permissions apply. Add a function for setting the region 0
access permissions.
Also add some VERBOSE logging and allow assembly files to include
the TZC header.
Change-Id: I4389261ba10a6e5e2e43ee93d55318dc507b6648
Dan Handley
committed
on 27 Apr 2015
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2015-04-13 |
Pass arguments/results between EL3/S-EL1 via CPU registers (x0-x7)
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This patch removes the need for a shared buffer between the EL3 and S-EL1
levels. We now use the CPU registers, x0-x7, while passing data between
the two levels. Since TLK is a 32-bit Trusted OS, tlkd has to unpack the
arguments in the x0-x7 registers. TLK in turn gets these values via r0-r7.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
authored
on 2 Apr 2015
Dan Handley
committed
on 13 Apr 2015
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2015-04-08 |
Add support to indicate size and end of assembly functions
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In order for the symbol table in the ELF file to contain the size of
functions written in assembly, it is necessary to report it to the
assembler using the .size directive.
To fulfil the above requirements, this patch introduces an 'endfunc'
macro which contains the .endfunc and .size directives. It also adds
a .func directive to the 'func' assembler macro.
The .func/.endfunc have been used so the assembler can fail if
endfunc is omitted.
Fixes ARM-Software/tf-issues#295
Change-Id: If8cb331b03d7f38fe7e3694d4de26f1075b278fc
Signed-off-by: Kévin Petit <kevin.petit@arm.com>
Kévin Petit
committed
on 8 Apr 2015
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2015-04-01 |
Merge pull request #277 from soby-mathew/sm/coh_lock_opt
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Optimize the bakery lock implementation
danh-arm
committed
on 1 Apr 2015
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Merge pull request #280 from vwadekar/tlkd-fixed-v3
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TLK dispatcher
danh-arm
committed
on 1 Apr 2015
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2015-03-31 |
Open/Close TA sessions, send commands/events to TAs
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This patch adds support to open/close secure sessions with Trusted
Apps and later send commands/events. Modify TLK_NUM_FID to indicate
the total number of FIDs available to the NS world.
Change-Id: I3f1153dfa5510bd44fc25f1fee85cae475b1abf1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 31 Mar 2015
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Preempt/Resume standard function ID calls
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This patch allows servicing of the non-secure world IRQs when the
CPU is in the secure world. Once the interrupt is handled, the
non-secure world issues the Resume FID to allow the secure payload
complete the preempted standard FID.
Change-Id: Ia52c41adf45014ab51d8447bed6605ca2f935587
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 31 Mar 2015
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Translate secure/non-secure virtual addresses
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This patch adds functionality to translate virtual addresses from
secure or non-secure worlds. This functionality helps Trusted Apps
to share virtual addresses directly and allows the NS world to
pass virtual addresses to TLK directly.
Change-Id: I77b0892963e0e839c448b5d0532920fb7e54dc8e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 31 Mar 2015
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Register NS shared memory for SP's activity logs and TA sessions
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This patch registers NS memory buffer with the secure payload using
two different functions IDs - REGISTER_LOGBUF, REGISTER_REQBUF.
a. The SP uses the log-buffer to store its activity logs, in a
pre-decided format. This helps in debugging secure payload's issues.
b. The SP uses the req-buffer to get the parameters required by
sessions with Trusted Applications.
Change-Id: I6b0247cf7790524132ee0da24f1f35b1fccec5d5
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 31 Mar 2015
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Add TLK Dispatcher (tlkd) based on the Test Dispatcher (tspd)
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TLK Dispatcher (tlkd) is based on the tspd and is the glue required
to run TLK as a Secure Payload with the Trusted Firmware.
Change-Id: I69e573d26d52342eb049feef773dd7d2a506f4ab
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 31 Mar 2015
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2015-03-27 |
Remove the `owner` field in bakery_lock_t data structure
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This patch removes the `owner` field in bakery_lock_t structure which
is the data structure used in the bakery lock implementation that uses
coherent memory. The assertions to protect against recursive lock
acquisition were based on the 'owner' field. They are now done based
on the bakery lock ticket number. These assertions are also added
to the bakery lock implementation that uses normal memory as well.
Change-Id: If4850a00dffd3977e218c0f0a8d145808f36b470
Soby Mathew
committed
on 27 Mar 2015
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Optimize the bakery lock structure for coherent memory
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This patch optimizes the data structure used with the bakery lock
implementation for coherent memory to save memory and minimize memory
accesses. These optimizations were already part of the bakery lock
implementation for normal memory and this patch now implements
it for the coherent memory implementation as well. Also
included in the patch is a cleanup to use the do-while loop while
waiting for other contenders to finish choosing their tickets.
Change-Id: Iedb305473133dc8f12126726d8329b67888b70f1
Soby Mathew
committed
on 27 Mar 2015
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2015-03-19 |
Merge pull request #270 from vikramkanigiri/vk/a72_cpu_support
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Add support for ARM Cortex-A72 processor
danh-arm
committed
on 19 Mar 2015
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2015-03-18 |
Add support for ARM Cortex-A72 processor
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This patch adds support for ARM Cortex-A72 processor in the CPU
specific framework.
Change-Id: I5986855fc1b875aadf3eba8c36e989d8a05e5175
Vikram Kanigiri
committed
on 18 Mar 2015
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2015-03-17 |
Merge pull request #269 from vikramkanigiri/vk/common-cci
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Common driver for ARM cache coherent Interconnects
danh-arm
committed
on 17 Mar 2015
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Merge pull request #268 from vikramkanigiri/vk/move_init_cpu_ops
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Initialise cpu ops after enabling data cache
danh-arm
committed
on 17 Mar 2015
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2015-03-16 |
Use ARM CCI driver on FVP and Juno platforms
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This patch updates the FVP and Juno platform ports to use the common
driver for ARM Cache Coherent Interconnects.
Change-Id: Ib142f456b9b673600592616a2ec99e9b230d6542
Vikram Kanigiri
committed
on 16 Mar 2015
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Common driver for ARM Cache Coherent Interconnects
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Even though both CCI-400 and CCI-500 IPs have different configurations
with respect to the number and types of supported interfaces, their
register offsets and programming sequences are similar. This patch
creates a common driver for enabling and disabling snoop transactions
and DVMs with both the IPs.
New platform ports which implement one of these IPs should use this
common driver. Existing platform ports which implement CCI-400 should
migrate to the common driver as the standalone CCI-400 will be
deprecated in the future.
Change-Id: I3ccd0eb7b062922d2e4a374ff8c21e79fa357556
Vikram Kanigiri
committed
on 16 Mar 2015
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Add macro to calculate number of elements in an array
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This patch defines the ARRAY_SIZE macro for calculating number of elements
in an array and uses it where appropriate.
Change-Id: I72746a9229f0b259323972b498b9a3999731bc9b
Vikram Kanigiri
committed
on 16 Mar 2015
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