intel: Update RSU driver return code ...

Modify RSU driver error code for backward-compatibility with
Linux RSU driver

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib9e38d4017efe35d3aceeee27dce451fbd429fb5

Merge "Modify multithreaded dts file of DynamIQ FVPs" into integration

Merge "change-log: Add fconf entry" into integration

Merge "Build: fix 'BL stage' comment for build macros" into integration

Build: fix 'BL stage' comment for build macros ...

The MAKE_BL macro is invoked for 1, 2, 2u, 31, 32.

Fix the comments.

Change-Id: I35dd25cc2ea13885c184fb9c8229a322b33f7e71
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Merge "amlogic/axg: Add documentation page to the index" into integration

amlogic/axg: Add documentation page to the index ...

It is needed to make it appear in the table of contents. Right now,
all Amlogic documentation pages appear under the "Platform ports"
section, except the AXG one.

Change-Id: Ibcfc3b156888d2a9574953578978b629e185c708
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

change-log: Add fconf entry ...

Change-Id: I6686f172d0c24f6c457a39cdf4debcbf05475540
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

Modify multithreaded dts file of DynamIQ FVPs ...

The dts file now contains a CPU map that precisely describes the
topology including thread nodes. The map was also extended to have 16
PEs to be able to test multithreaded FVPs with 8 cores in the same
cluster.

Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: If39559b05d20bfd68d0ecf830ddcbc5233b288a0

Merge "tools: Small improvement to print_memory_map script" into integration

Merge "uniphier: prepare uniphier_soc_info() for next SoC" into integration

Merge "FVP: Fix incorrect GIC mapping" into integration

Merge "allwinner: Implement PSCI system suspend using SCPI" into integration

Merge "allwinner: Add a msgbox driver for use with SCPI" into integration

uniphier: prepare uniphier_soc_info() for next SoC ...

The revision register address will be changed in the next SoC.

The LSI revision is needed in order to know where the revision
register is located, but you need to read out the revision
register for that. This is impossible.

We need to know the revision register address by other means.
Use BL_CODE_BASE, where the base address of the TF image that is
currently running. If it is bigger than 0x80000000 (i.e. the DRAM
base is 0x80000000), we assume it is a legacy SoC.

Change-Id: I9d7f4325fe2085a8a1ab5310025e5948da611256
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Merge "allwinner: Reserve and map space for the SCP firmware" into integration

Merge "plat: imx8m: Fix the rdc memory region slot's offset" into integration

Merge changes from topic "console_t_cleanup" into integration ...

* changes:
  marvell: Consolidate console register calls
  uniphier: Use generic console_t data structure
  spe: Use generic console_t data structure
  LS 16550: Use generic console_t data structure
  stm32: Use generic console_t data structure
  rcar: Use generic console_t data structure
  a3700: Use generic console_t data structure
  16550: Use generic console_t data structure
  imx: Use generic console_t data structure

Merge changes from topic "console_t_cleanup" into integration ...

* changes:
  coreboot: Use generic base address
  skeletton: Use generic console_t data structure
  cdns: Use generic console_t data structure

Merge "pl011: Use generic console_t data structure" into integration

Merge "meson: Use generic console_t data structure" into integration

Merge "console: Integrate UART base address in generic console_t" into integration

Merge "allwinner: Adjust SRAM A2 base to include the ARISC vectors" into integration

Merge "arm/css/scpi: Don't panic if the SCP fails to respond" into integration

Merge "Read-only xlat tables for BL31 memory" into integration

FVP: Fix incorrect GIC mapping ...

This patch fixes incorrect setting for DEVICE1_SIZE
for FVP platforms with more than 8 PEs.
The current value of 0x200000 supports only 8 PEs
and causes exception for FVP platforms with the greater
number of PEs, e.g. FVP_Base_Cortex_A65AEx8 with 16 PEs
in one cluster.

Change-Id: Ie6391509fe6eeafb8ba779303636cd762e7d21b2
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

Merge "mediatek: mt8183: protect 4GB~8GB dram memory" into integration

Merge "SPMD: generate and add Secure Partition blobs into FIP" into integration

Merge "uniphier: make on-chip SRAM region configurable" into integration

marvell: Consolidate console register calls ...

Now that different UARTs share the same console_t struct, we can
simplify the console selection for the Marvell platforms:
We share the same console_t pointers, just change the name of the
console register functions, depending on the selected platform.

Change-Id: I6fe3e49fd7f208a9b3372c5deef43236a12867bc
Signed-off-by: Andre Przywara <andre.przywara@arm.com>