2015-08-13 |
PSCI: Introduce new platform and CM helper APIs
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This patch introduces new platform APIs and context management helper APIs
to support the new topology framework based on linear core position. This
framework will be introduced in the follwoing patch and it removes the
assumption that the MPIDR based affinity levels map directly to levels
in a power domain tree. The new platforms APIs and context management
helpers based on core position are as described below:
* plat_my_core_pos() and plat_core_pos_by_mpidr()
These 2 new mandatory platform APIs are meant to replace the existing
'platform_get_core_pos()' API. The 'plat_my_core_pos()' API returns the
linear index of the calling core and 'plat_core_pos_by_mpidr()' returns
the linear index of a core specified by its MPIDR. The latter API will also
validate the MPIDR passed as an argument and will return an error code (-1)
if an invalid MPIDR is passed as the argument. This enables the caller to
safely convert an MPIDR of another core to its linear index without querying
the PSCI topology tree e.g. during a call to PSCI CPU_ON.
Since the 'plat_core_pos_by_mpidr()' API verifies an MPIDR, which is always
platform specific, it is no longer possible to maintain a default implementation
of this API. Also it might not be possible for a platform port to verify an
MPIDR before the C runtime has been setup or the topology has been initialized.
This would prevent 'plat_core_pos_by_mpidr()' from being callable prior to
topology setup. As a result, the generic Trusted Firmware code does not call
this API before the topology setup has been done.
The 'plat_my_core_pos' API should be able to run without a C runtime.
Since this API needs to return a core position which is equal to the one
returned by 'plat_core_pos_by_mpidr()' API for the corresponding MPIDR,
this too cannot have default implementation and is a mandatory API for
platform ports. These APIs will be implemented by the ARM reference platform
ports later in the patch stack.
* plat_get_my_stack() and plat_set_my_stack()
These APIs are the stack management APIs which set/return stack addresses
appropriate for the calling core. These replace the 'platform_get_stack()' and
'platform_set_stack()' APIs. A default weak MP version and a global UP version
of these APIs are provided for the platforms.
* Context management helpers based on linear core position
A set of new context management(CM) helpers viz cm_get_context_by_index(),
cm_set_context_by_index(), cm_init_my_context() and cm_init_context_by_index()
are defined which are meant to replace the old helpers which took MPIDR
as argument. The old CM helpers are implemented based on the new helpers to
allow for code consolidation and will be deprecated once the switch to the new
framework is done.
Change-Id: I89758632b370c2812973a4b2efdd9b81a41f9b69
Soby Mathew
authored
on 9 Apr 2015
Achin Gupta
committed
on 13 Aug 2015
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2015-08-12 |
Merge pull request #360 from vwadekar/tegra-platform-def-v2
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Tegra: fix PLATFORM_{MAX_AFFLVL|CORE_COUNT|NUM_AFFS} macros
danh-arm
committed
on 12 Aug 2015
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Merge pull request #357 from vwadekar/tegra-bl31-memmap-fix
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Tegra: memmap the actual memory available for BL31
danh-arm
committed
on 12 Aug 2015
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2015-08-11 |
Tegra: fix PLATFORM_{CORE_COUNT|NUM_AFFS} macros
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This patch fixes the following macros for Tegra SoCs.
* PLATFORM_CORE_COUNT: PLATFORM_CLUSTER_COUNT * PLATFORM_MAX_CPUS_PER_CLUSTER
* PLATFORM_NUM_AFFS: PLATFORM_CORE_COUNT + PLATFORM_CLUSTER_COUNT + 1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 11 Aug 2015
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Merge pull request #356 from mtk09422/mt8173-support-v3
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Mt8173 support v3
danh-arm
committed
on 11 Aug 2015
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Tegra: memmap the actual memory available for BL31
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On Tegra SoCs, the TZDRAM contains the BL31 and BL32 images. This patch
uses only the actual memory available for BL31 instead of mapping the
entire TZDRAM.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 11 Aug 2015
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Initial platform port for MediaTek mt8173
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- Boot up 4 cores.
- Add a generic UART driver.
- Add generic CPU helper functions
- Supoort suspend
- Add system_off & system_reset implementation
- Add crash console reporting implementation
- Add get_sys_suspend_power_state() for PSCI 1.0 SYSTEM_SUSPEND
- Add Mediatek SIP runtime service
- Add delay timer platform implementation
Change-Id: I44138249f115ee10b9cbd26fdbc2dd3af04d825f
Signed-off-by: CC Ma <cc.ma@mediatek.com>
Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
CC Ma
authored
on 13 Apr 2015
Yidi Lin
committed
on 11 Aug 2015
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2015-08-05 |
PSCI: Remove references to affinity based power management
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As per Section 4.2.2. in the PSCI specification, the term "affinity"
is used in the context of describing the hierarchical arrangement
of cores. This often, but not always, maps directly to the processor
power domain topology of the system. The current PSCI implementation
assumes that this is always the case i.e. MPIDR based levels of
affinity always map to levels in a power domain topology tree.
This patch is the first in a series of patches which remove this
assumption. It removes all occurences of the terms "affinity
instances and levels" when used to describe the power domain
topology. Only the terminology is changed in this patch. Subsequent
patches will implement functional changes to remove the above
mentioned assumption.
Change-Id: Iee162f051b228828310610c5a320ff9d31009b4e
Soby Mathew
committed
on 5 Aug 2015
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PSCI: Invoke PM hooks only for the highest level
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This patch optimizes the invocation of the platform power management hooks for
ON, OFF and SUSPEND such that they are called only for the highest affinity
level which will be powered off/on. Earlier, the hooks were being invoked for
all the intermediate levels as well.
This patch requires that the platforms migrate to the new semantics of the PM
hooks. It also removes the `state` parameter from the pm hooks as the `afflvl`
parameter now indicates the highest affinity level for which power management
operations are required.
Change-Id: I57c87931d8a2723aeade14acc710e5b78ac41732
Soby Mathew
committed
on 5 Aug 2015
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PSCI: Create new directory to implement new frameworks
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This patch creates a copy of the existing PSCI files and related psci.h and
platform.h header files in a new `PSCI1.0` directory. The changes for the
new PSCI power domain topology and extended state-ID frameworks will be
added incrementally to these files. This incremental approach will
aid in review and in understanding the changes better. Once all the
changes have been introduced, these files will replace the existing PSCI
files.
Change-Id: Ibb8a52e265daa4204e34829ed050bddd7e3316ff
Soby Mathew
committed
on 5 Aug 2015
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cortex_a53: Add A53 errata #826319, #836870
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- Apply a53 errata #826319 to revision <= r0p2
- Apply a53 errata #836870 to revision <= r0p3
- Update docs/cpu-specific-build-macros.md for newly added errata build flags
Change-Id: I44918e36b47dca1fa29695b68700ff9bf888865e
Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Jimmy Huang
authored
on 29 Jul 2015
Yidi Lin
committed
on 5 Aug 2015
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Add mmio utility functions
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- Add mmio 16 bits read/write functions.
- Add clear/set/clear-and-set utility functions.
Change-Id: I00fdbdf24af537424f8666b1cadaa5f77a2a46ed
Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Jimmy Huang
authored
on 31 Jul 2015
Yidi Lin
committed
on 5 Aug 2015
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Fix build error with optimizations disabled (-O0)
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If Trusted Firmware is built with optimizations disabled (-O0), the
linker throws the following error:
undefined reference to 'xxx'
Where 'xxx' is a raw inline function defined in a header file. The
reason is that, with optimizations disabled, GCC may decide to skip
the inlining. If that is the case, an external definition to the
compilation unit must be provided. Because no external definition
is present, the linker throws the error.
This patch fixes the problem by declaring the following inline
functions static, so the internal definition is used:
inline void soc_css_security_setup(void)
inline const arm_config_t *get_arm_config(void)
Change-Id: Id650d6be1b1396bdb48af1ac8a4c7900d212e95f
Juan Castillo
committed
on 5 Aug 2015
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2015-08-04 |
Merge pull request #351 from davwan01/davwan01/docs-update
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Some minor fixes to interrupt-framework-design.md
danh-arm
committed
on 4 Aug 2015
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Merge pull request #349 from jcastillo-arm/jc/tbb_cert_opt
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TBB: rework cert_create tool to follow a data driven approach
danh-arm
committed
on 4 Aug 2015
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Merge pull request #348 from vwadekar/bootargs-tzdram-base-v2
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Bootargs tzdram base v2
danh-arm
committed
on 4 Aug 2015
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Some minor fixes to interrupt-framework-design.md
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This patch fixes a pair of typos. The security state had been described
as non-secure where it should have been secure.
Change-Id: Ib3f424708a6b8e2084e5447f8507ea4e9c99ee79
David Wang
committed
on 4 Aug 2015
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2015-08-01 |
docs: fix the command to compile BL31 on Tegra
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This patch fixes the command line used to compile BL31 on
Tegra platforms.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 1 Aug 2015
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2015-07-31 |
Tegra132: set TZDRAM_BASE to 0xF5C00000
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The TZDRAM base on the reference platform has been bumped up due to
some BL2 memory cleanup. Platforms can also use a different TZDRAM
base by setting TZDRAM_BASE=<value> in the build command line.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 31 Jul 2015
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Tegra: retrieve BL32's bootargs from bl32_ep_info
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This patch removes the bootargs pointer from the platform params
structure. Instead the bootargs are passed by the BL2 in the
bl32_ep_info struct which is a part of the EL3 params struct.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 31 Jul 2015
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2015-07-28 |
Merge pull request #344 from vwadekar/tegra-mselect-restore-v2
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Tegra210: enable WRAP to INCR burst type conversions
danh-arm
committed
on 28 Jul 2015
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2015-07-27 |
Tegra210: enable WRAP to INCR burst type conversions
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The Memory Select Switch Controller routes any CPU transactions to
the appropriate slave depending on the transaction address. During
system suspend, it loses all config settings and hence the CPU has
to restore them during resume.
This patch restores the controller's settings for enabling WRAP to
INCR burst type conversions on the master ports, for any incoming
requests from the AXI slave ports.
Tested by performing multiple system suspend cycles.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 27 Jul 2015
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2015-07-24 |
Merge pull request #342 from vwadekar/tlkd-delete-need-bl32-v1
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tlkd: delete 'NEED_BL32' build variable
danh-arm
committed
on 24 Jul 2015
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tlkd: delete 'NEED_BL32' build variable
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Remove the 'NEED_BL32' flag from the makefile. TLK compiles using a
completely different build system and is present on the device as a
binary blob. The NEED_BL32 flag does not influence the TLK load/boot
sequence at all. Moreover, it expects that TLK binary be present on
the host before we can compile BL31 support for Tegra.
This patch removes the flag from the makefile and thus decouples both
the build systems.
Tested by booting TLK without the NEED_BL32 flag.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 24 Jul 2015
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Merge pull request #341 from vwadekar/tegra-denver-plat-support-v3
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Tegra denver plat support v3
danh-arm
committed
on 24 Jul 2015
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2015-07-23 |
Tegra: modify 'BUILD_PLAT' to point to soc specific build dirs
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This patch modifies the 'BUILD_PLAT' makefile variable to point to the soc
specific build directory in order to allow each Tegra soc to have its own
build directory. This way we can keep the build outputs separate and can
keep multiple soc specific builds alive at the same time.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 23 Jul 2015
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Tegra: Support for Tegra's T132 platforms
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This patch implements support for T132 (Denver CPU) based Tegra
platforms.
The following features have been added:
* SiP calls to switch T132 CPU's AARCH mode
* Complete PSCI support, including 'System Suspend'
* Platform specific MMIO settings
* Locking of CPU vector registers
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 23 Jul 2015
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Add "Project Denver" CPU support
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Denver is NVIDIA's own custom-designed, 64-bit, dual-core CPU which is
fully ARMv8 architecture compatible. Each of the two Denver cores
implements a 7-way superscalar microarchitecture (up to 7 concurrent
micro-ops can be executed per clock), and includes a 128KB 4-way L1
instruction cache, a 64KB 4-way L1 data cache, and a 2MB 16-way L2
cache, which services both cores.
Denver implements an innovative process called Dynamic Code Optimization,
which optimizes frequently used software routines at runtime into dense,
highly tuned microcode-equivalent routines. These are stored in a
dedicated, 128MB main-memory-based optimization cache. After being read
into the instruction cache, the optimized micro-ops are executed,
re-fetched and executed from the instruction cache as long as needed and
capacity allows.
Effectively, this reduces the need to re-optimize the software routines.
Instead of using hardware to extract the instruction-level parallelism
(ILP) inherent in the code, Denver extracts the ILP once via software
techniques, and then executes those routines repeatedly, thus amortizing
the cost of ILP extraction over the many execution instances.
Denver also features new low latency power-state transitions, in addition
to extensive power-gating and dynamic voltage and clock scaling based on
workloads.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 23 Jul 2015
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Tegra: implement per-SoC validate_power_state() handler
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The validate_power_state() handler checks the power_state for a valid afflvl
and state id. Although the afflvl check is common, the state ids are implementation
defined.
This patch moves the handler to the tegra/soc folder to allow each SoC to validate
the power_state for supported parameters.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 23 Jul 2015
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Tegra: T210: include CPU files from SoC's platform.mk
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This patch moves the inclusion of CPU code (A53, A57) to T210's
makefile. This way we can reduce code size for Tegra platforms by
including only the required CPU files.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 23 Jul 2015
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