2014-06-05 |
juno: Fix build errors due to recent changes
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This is a miscellaneous commit that fixes all build
errors introduced by the rebase of the Juno codebase
on the latest trusted firmware.
- Make codebase consistent in its use of #include "" syntax
for user includes and #include <> syntax for system includes.
- Sort header files alphabetically
- Use tag names for structure types.
Replace instances of the former io_handle and io_dev_handle
types with uintptr_t.
- Review the .c and .S files for which header files really need
including and reorder the #include statements alphabetically.
Change-Id: I1d409fafb6dc257a38992ee15b22b0e890d040b0
Sandrine Bailleux
committed
on 5 Jun 2014
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2014-06-04 |
Enable Debug and SError exceptions on warm boot path
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Enable Debug and SError exceptions:
- when receiving an SMC;
- when a CPU is physically powered up (upon resumption from suspend
or in response to a PSCI cpu_on call)
Change-Id: I7e5613e34034be6ed68ec9e2aef4de66aa5ac65e
Sandrine Bailleux
committed
on 4 Jun 2014
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Do not route external abort and SError interrupts to EL3
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The software running at a given exception level should handle
external aborts and SError interrupts itself.
Change-Id: Ic249fdf8472e0c64306ce3913562a2ac89c78627
Sandrine Bailleux
committed
on 4 Jun 2014
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Workaround: Setup register context for BL3-3
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This is a temporary solution for issue #20
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Jon Medhurst
authored
on 19 Feb 2014
Sandrine Bailleux
committed
on 4 Jun 2014
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2014-05-29 |
Merge pull request #111 'soby-mathew-sm:fix_cookie_to_int_handler'
Dan Handley
committed
on 29 May 2014
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Fix compilation issue for IMF_READ_INTERRUPT_ID build flag
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This patch fixes the compilation issue for trusted firmware when the
IMF_READ_INTERRUPT_ID is enabled.
Change-Id: I94ab613b9bc96a7c1935796c674dc42246aaafee
Soby Mathew
committed
on 29 May 2014
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Pass 'cookie' parameter to interrupt handler in BL3-1
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The interrupt handling routine in BL3-1 expects a cookie as its last
parameter which was not being passed when invoking the interrupt
handler in BL3-1. This patch fixes that by passing a dummy cookie
parameter in the x3 register.
Fixes ARM-software/tf-issues#171
Change-Id: Ic98abbbd9f849e6f1c55343e865b5e0a4904a1c5
Soby Mathew
committed
on 29 May 2014
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2014-05-28 |
Pass the args to the BL3-3 entrypoint
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At present the arguments for BL3-3 in the entry_point_info
structure are not being transferred to X0-X7 before starting
execution of this image
This patch saves the args for BL3-3 into cpu context used
for its entry
Fixes ARM-software/tf-issues#172
Change-Id: I001b4b9bff6a264336f0d01d377619ae719f928b
Vikram Kanigiri
committed
on 28 May 2014
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2014-05-27 |
Further renames of platform porting functions
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Rename the ic_* platform porting functions to plat_ic_* to be
consistent with the other functions in platform.h. Also rename
bl31_get_next_image_info() to bl31_plat_get_next_image_ep_info()
and remove the duplicate declaration in bl31.h.
Change-Id: I4851842069d3cff14c0a468daacc0a891a7ede84
Dan Handley
committed
on 27 May 2014
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2014-05-23 |
Move BL porting functions into platform.h
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Some platform porting functions were in BL specific header files.
These have been moved to platform.h so that all porting functions
are in the same place. The functions are now grouped by BL.
Obsolete BL headers files have been removed.
Also, the weak declaration of the init_bl2_mem_layout() function
has been moved out the header file and into the source file
(bl_common.c) using the more succinct #pragma syntax. This
mitigates the risk of 2 weak definitions being created and the
wrong one being picked up by the compiler.
Change-Id: Ib19934939fd755f3e5a5a5bceec88da684308a83
Dan Handley
authored
on 15 May 2014
Achin Gupta
committed
on 23 May 2014
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Split platform.h into separate headers
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Previously, platform.h contained many declarations and definitions
used for different purposes. This file has been split so that:
* Platform definitions used by common code that must be defined
by the platform are now in platform_def.h. The exact include
path is exported through $PLAT_INCLUDES in the platform makefile.
* Platform definitions specific to the FVP platform are now in
/plat/fvp/fvp_def.h.
* Platform API declarations specific to the FVP platform are now
in /plat/fvp/fvp_private.h.
* The remaining platform API declarations that must be ported by
each platform are still in platform.h but this file has been
moved to /include/plat/common since this can be shared by all
platforms.
Change-Id: Ieb3bb22fbab3ee8027413c6b39a783534aee474a
Dan Handley
authored
on 14 May 2014
Achin Gupta
committed
on 23 May 2014
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Merge pull request #101 from sandrine-bailleux:sb/tf-issue-81-v2
Andrew Thoelke
committed
on 23 May 2014
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Make the memory layout more flexible
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Currently the platform code gets to define the base address of each
boot loader image. However, the linker scripts couteract this
flexibility by enforcing a fixed overall layout of the different
images. For example, they require that the BL3-1 image sits below
the BL2 image. Choosing BL3-1 and BL2 base addresses in such a way
that it violates this constraint makes the build fail at link-time.
This patch requires the platform code to now define a limit address
for each image. The linker scripts check that the image fits within
these bounds so they don't rely anymore on the position of a given
image in regard to the others.
Fixes ARM-software/tf-issues#163
Change-Id: I8c108646825da19a6a8dfb091b613e1dd4ae133c
Sandrine Bailleux
committed
on 23 May 2014
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Merge pull request #105 from athoelke:sm/support_normal_irq_in_tsp-v2
Andrew Thoelke
committed
on 23 May 2014
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Merge pull request #102 from achingupta:ag/tf-issues#104-v2
Andrew Thoelke
committed
on 23 May 2014
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Merge pull request #99 from vikramkanigiri:vk/tf-issues-133_V3
Andrew Thoelke
committed
on 23 May 2014
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Non-Secure Interrupt support during Standard SMC processing in TSP
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Implements support for Non Secure Interrupts preempting the
Standard SMC call in EL1. Whenever an IRQ is trapped in the
Secure world we securely handover to the Normal world
to process the interrupt. The normal world then issues
"resume" smc call to resume the previous interrupted SMC call.
Fixes ARM-software/tf-issues#105
Change-Id: I72b760617dee27438754cdfc9fe9bcf4cc024858
Soby Mathew
authored
on 9 May 2014
Andrew Thoelke
committed
on 23 May 2014
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2014-05-22 |
Introduce interrupt handling framework in BL3-1
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This patch adds a common handler for FIQ and IRQ exceptions in the
BL3-1 runtime exception vector table. This function determines the
interrupt type and calls its handler. A crash is reported if an
inconsistency in the interrupt management framework is detected. In
the event of a spurious interrupt, execution resumes from the
instruction where the interrupt was generated.
This patch also removes 'cm_macros.S' as its contents have been moved
to 'runtime_exceptions.S'
Change-Id: I3c85ecf8eaf43a3fac429b119ed0bd706d2e2093
Achin Gupta
committed
on 22 May 2014
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Introduce interrupt registration framework in BL3-1
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This patch introduces a framework for registering interrupts routed to
EL3. The interrupt routing model is governed by the SCR_EL3.IRQ and
FIQ bits and the security state an interrupt is generated in. The
framework recognizes three type of interrupts depending upon which
exception level and security state they should be handled in
i.e. Secure EL1 interrupts, Non-secure interrupts and EL3
interrupts. It provides an API and macros that allow a runtime service
to register an handler for a type of interrupt and specify the routing
model. The framework validates the routing model and uses the context
management framework to ensure that it is applied to the SCR_EL3 prior
to entry into the target security state. It saves the handler in
internal data structures. An API is provided to retrieve the handler
when an interrupt of a particular type is asserted. Registration is
expected to be done once by the primary CPU. The same handler and
routing model is used for all CPUs.
Support for EL3 interrupts will be added to the framework in the
future. A makefile flag has been added to allow the FVP port choose
between ARM GIC v2 and v3 support in EL3. The latter version is
currently unsupported.
A framework for handling interrupts in BL3-1 will be introduced in
subsequent patches. The default routing model in the absence of any
handlers expects no interrupts to be routed to EL3.
Change-Id: Idf7c023b34fcd4800a5980f2bef85e4b5c29e649
Achin Gupta
committed
on 22 May 2014
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Add context library API to change a bit in SCR_EL3
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This patch adds an API to write to any bit in the SCR_EL3 member of
the 'cpu_context' structure of the current CPU for a specified
security state. This API will be used in subsequent patches which
introduce interrupt management in EL3 to specify the interrupt routing
model when execution is not in EL3.
It also renames the cm_set_el3_elr() function to cm_set_elr_el3()
which is more in line with the system register name being targeted by
the API.
Change-Id: I310fa7d8f827ad3f350325eca2fb28cb350a85ed
Achin Gupta
committed
on 22 May 2014
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Add support for BL3-1 as a reset vector
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This change adds optional reset vector support to BL3-1
which means BL3-1 entry point can detect cold/warm boot,
initialise primary cpu, set up cci and mail box.
When using BL3-1 as a reset vector it is assumed that
the BL3-1 platform code can determine the location of
the BL3-2 images, or load them as there are no parameters
that can be passed to BL3-1 at reset.
It also fixes the incorrect initialisation of mailbox
registers on the FVP platform
This feature can be enabled by building the code with
make variable RESET_TO_BL31 set as 1
Fixes ARM-software/TF-issues#133
Fixes ARM-software/TF-issues#20
Change-Id: I4e23939b1c518614b899f549f1e8d412538ee570
Vikram Kanigiri
committed
on 22 May 2014
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Rework memory information passing to BL3-x images
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The issues addressed in this patch are:
1. Remove meminfo_t from the common interfaces in BL3-x,
expecting that platform code will find a suitable mechanism
to determine the memory extents in these images and provide
it to the BL3-x images.
2. Remove meminfo_t and bl31_plat_params_t from all FVP BL3-x
code as the images use link-time information to determine
memory extents.
meminfo_t is still used by common interface in BL1/BL2 for
loading images
Change-Id: I4e825ebf6f515b59d84dc2bdddf6edbf15e2d60f
Vikram Kanigiri
committed
on 22 May 2014
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Populate BL31 input parameters as per new spec
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This patch is based on spec published at
https://github.com/ARM-software/tf-issues/issues/133
It rearranges the bl31_args struct into
bl31_params and bl31_plat_params which provide the
information needed for Trusted firmware and platform
specific data via x0 and x1
On the FVP platform BL3-1 params and BL3-1 plat params
and its constituents are stored at the start of TZDRAM.
The information about memory availability and size for
BL3-1, BL3-2 and BL3-3 is moved into platform specific data.
Change-Id: I8b32057a3d0dd3968ea26c2541a0714177820da9
Vikram Kanigiri
committed
on 22 May 2014
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Rework handover interface between BL stages
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This patch reworks the handover interface from: BL1 to BL2 and
BL2 to BL3-1. It removes the raise_el(), change_el(), drop_el()
and run_image() functions as they catered for code paths that were
never exercised.
BL1 calls bl1_run_bl2() to jump into BL2 instead of doing the same
by calling run_image(). Similarly, BL2 issues the SMC to transfer
execution to BL3-1 through BL1 directly. Only x0 and x1 are used
to pass arguments to BL31. These arguments and parameters for
running BL3-1 are passed through a reference to a
'el_change_info_t' structure. They were being passed value in
general purpose registers earlier.
Change-Id: Id4fd019a19a9595de063766d4a66295a2c9307e1
Vikram Kanigiri
committed
on 22 May 2014
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Merge pull request #83 from athoelke/at/tf-issues-126
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Set SCR_EL3.RW correctly before exiting bl31_main
Andrew Thoelke
committed
on 22 May 2014
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2014-05-19 |
Merge pull request #78 from jeenuv:tf-issues-148
Andrew Thoelke
committed
on 19 May 2014
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2014-05-16 |
Add build configuration for timer save/restore
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At present, non-secure timer register contents are saved and restored as
part of world switch by BL3-1. This effectively means that the
non-secure timer stops, and non-secure timer interrupts are prevented
from asserting until BL3-1 switches back, introducing latency for
non-secure services. Often, secure world might depend on alternate
sources for secure interrupts (secure timer or platform timer) instead
of non-secure timers, in which case this save and restore is
unnecessary.
This patch introduces a boolean build-time configuration NS_TIMER_SWITCH
to choose whether or not to save and restore non-secure timer registers
upon world switch. The default choice is made not to save and restore
them.
Fixes ARM-software/tf-issues#148
Change-Id: I1b9d623606acb9797c3e0b02fb5ec7c0a414f37e
Jeenu Viswambharan
committed
on 16 May 2014
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Set SCR_EL3.RW correctly before exiting bl31_main
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SCR_EL3.RW was not updated immediately before exiting bl31_main() and
running BL3-3. If a AArch32 Secure-EL1 Payload had just been
initialised, then the SCR_EL3.RW bit would be left indicating a
32-bit BL3-3, which may not be correct.
This patch explicitly sets SCR_EL3.RW appropriately based on the
provided SPSR_EL3 value for the BL3-3 image.
Fixes ARM-software/tf-issues#126
Change-Id: Ic7716fe8bc87e577c4bfaeb46702e88deedd9895
Andrew Thoelke
committed
on 16 May 2014
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Rework BL3-1 unhandled exception handling and reporting
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This patch implements the register reporting when unhandled exceptions are
taken in BL3-1. Unhandled exceptions will result in a dump of registers
to the console, before halting execution by that CPU. The Crash Stack,
previously called the Exception Stack, is used for this activity.
This stack is used to preserve the CPU context and runtime stack
contents for debugging and analysis.
This also introduces the per_cpu_ptr_cache, referenced by tpidr_el3,
to provide easy access to some of BL3-1 per-cpu data structures.
Initially, this is used to provide a pointer to the Crash stack.
panic() now prints the the error file and line number in Debug mode
and prints the PC value in release mode.
The Exception Stack is renamed to Crash Stack with this patch.
The original intention of exception stack is no longer valid
since we intend to support several valid exceptions like IRQ
and FIQ in the trusted firmware context. This stack is now
utilized for dumping and reporting the system state when a
crash happens and hence the rename.
Fixes ARM-software/tf-issues#79 Improve reporting of unhandled exception
Change-Id: I260791dc05536b78547412d147193cdccae7811a
Soby Mathew
committed
on 16 May 2014
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2014-05-08 |
Merge pull request #63 from soby-mathew/sm/save_callee_saved_registers_in_cpu_context-1
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Preserve x19-x29 across world switch for exception handling
danh-arm
committed
on 8 May 2014
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