plat: imx8m: Add the aipstz init to config peripheral access ...

AIPSTZ provide access control for all the peripherals connected
to it. In this patch all the perperals are configured accessible
to all the master. it can be customized based the actual use
case.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I5ef5baa1da6906f13a60923d27ede336c61e319a

Merge "plat: imx8mq: Remove duplicated linker symbols" into integration

Merge "drivers: ufs: Extend the delay after reset to wait for some slower chips" into integration

Merge "Remove .arch directives from spinlock.S" into integration

Merge "SMMUv3: Abort DMA transactions" into integration

drivers: ufs: Extend the delay after reset to wait for some slower chips ...

We've seen issues with some THG based UFS chips, where
after reset the LUNs don't always enumerate properly.

After some debugging, we found that extending the mdelay
here seems to resolve the issue by giving the chips enough
time to complete reset.

Change-Id: I848f810b2438ed6ad3d33db614c61d2cef9ac400
Signed-off-by: John Stultz <john.stultz@linaro.org>

plat: imx8mq: Remove duplicated linker symbols ...

Remove duplicated linker symbols, resue the symbols
defined in bl_common.h

Change-Id: I10de450eccc78c09b61a8ae7126bf4f4029fa682
Signed-off-by: Jacky Bai <ping.bai@nxp.com>

Remove .arch directives from spinlock.S ...

This patch removes .arch "arm8.1-a" and "armv8-a"
directives which overwrite ASFLAGS_aarch64 option based
on ARM_ARCH_MINOR passed to Makefile and cause
translation errors like
"selected processor does not support `bti jc'"
for armv8.5-a targets when BTI support is enabled.

Change-Id: Idca5b66ed1e5d86e2188b0c0f16c3819990957c4
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

SMMUv3: Abort DMA transactions ...

For security DMA should be blocked at the SMMU by default
unless explicitly enabled for a device. SMMU is disabled
after reset with all streams bypassing the SMMU, and
abortion of all incoming transactions implements a default
deny policy on reset.
This patch also moves "bl1_platform_setup()" function from
arm_bl1_setup.c to FVP platforms' fvp_bl1_setup.c and
fvp_ve_bl1_setup.c files.

Change-Id: Ie0ffedc10219b1b884eb8af625bd4b6753749b1a
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

Merge "Initialize platform for MediaTek mt8183" into integration

Merge "maintainers: Step down as sub-maintainer" into integration

Merge "plat: imx8m: Implement IMX_SIP_BUILDINFO" into integration

Initialize platform for MediaTek mt8183 ...

- Add basic platform setup
- Add generic CPU helper functions
- Add delay timer platform implementation
- Use TI 16550 uart driver

Change-Id: I1c29569c68fe9fca5e10e88a22a29690bab7141f
Signed-off-by: kenny liang <kenny.liang@mediatek.com>

plat: imx8m: Implement IMX_SIP_BUILDINFO ...

The IMX_SIP_BUILDINFO call was implemented for imx8qm and imx8qx but
it's also applicable to imx8m.

This fixes U-Boot not printing commit hash on 8m with upstream TF-A.

Change-Id: Idcfd9729eaaccf329c24e241da325f1f6cd3c880
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>

maintainers: Step down as sub-maintainer ...

I'm giving full maintainership of the Raspberry Pi 3 platform port to
Paul. I'm also leaving the GXBB maintainership to Andre, who is also
happy to pass it on to someone else who is more interested in it.

Change-Id: Ieb2212f5fc11ebde9fc0c857e9e305d691d4ee3f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Merge "Add Makefile check for PAuth and AArch64" into integration

Add Makefile check for PAuth and AArch64 ...

Pointer authentication is supported only in AArch64. A relevant check is
added for that in the Makefile.

Change-Id: I021ba65a9bd5764fd33292bee42617015e04a870
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

Merge "docs: Update contribution guidelines for binary components" into integration

Merge changes I286b925e,I1151c2bc into integration ...

* changes:
  plat: imx8mq: Only keep IRQ 32 unmasked
  plat: imx8mq: gpc: Enable all power domain by default

Merge "Fix RST rendering and other typos" into integration

Fix RST rendering and other typos ...

1) One space was missing from the indentation and, hence, rendering error
was generated in the user guide.
2) Partially reword Pointer Authentication related info.

Change-Id: Id5e65d419ec51dd7764f24d1b96b6c9942d63ba4
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

plat: imx8mq: Only keep IRQ 32 unmasked ...

Only IRQ 32 (SPI 0) needs to be kept unmasked, not everything divisible
by 32.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Change-Id: I286b925eead89218cfeddd82f53a634f3447d212

plat: imx8mq: gpc: Enable all power domain by default ...

This is similar to imx8mm and allows uboot to run fastboot over USB otg.

There is a different set of power domains on 8mq but same bits covers
all off them.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Change-Id: I1151c2bc2d32b1e02b4db16285b3d30cabc0d64d

Merge changes from topic "sm/fix_a76_errata" into integration ...

* changes:
  Workaround for cortex-A76 errata 1286807
  Cortex-A76: workarounds for errata 1257314, 1262606, 1262888, 1275112

Workaround for cortex-A76 errata 1286807 ...

The workaround for Cortex-A76 errata #1286807 is implemented
in this patch.

Change-Id: I6c15af962ac99ce223e009f6d299cefb41043bed
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

Cortex-A76: workarounds for errata 1257314, 1262606, 1262888, 1275112 ...

The workarounds for errata 1257314, 1262606, 1262888 and 1275112 are
added to the Cortex-A76 cpu specific file. The workarounds are disabled
by default and have to be explicitly enabled by the platform integrator.

Change-Id: I70474927374cb67725f829d159ddde9ac4edc343
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

Merge "Add compile-time errors for HW_ASSISTED_COHERENCY flag" into integration

Add compile-time errors for HW_ASSISTED_COHERENCY flag ...

This patch fixes this issue:
https://github.com/ARM-software/tf-issues/issues/660

The introduced changes are the following:

1) Some cores implement cache coherency maintenance operation on the
hardware level. For those cores, such as - but not only - the DynamIQ
cores, it is mandatory that TF-A is compiled with the
HW_ASSISTED_COHERENCY flag. If not, the core behaviour at runtime is
unpredictable. To prevent this, compile time checks have been added and
compilation errors are generated, if needed.

2) To enable this change for FVP, a logical separation has been done for
the core libraries. A system cannot contain cores of both groups, i.e.
cores that manage coherency on hardware and cores that don't do it. As
such, depending on the HW_ASSISTED_COHERENCY flag, FVP includes the
libraries only of the relevant cores.

3) The neoverse_e1.S file has been added to the FVP sources.

Change-Id: I787d15819b2add4ec0d238249e04bf0497dc12f3
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

Merge "SMMUv3: refactor the driver code" into integration

SMMUv3: refactor the driver code ...

This patch is a preparation for the subsequent changes in
SMMUv3 driver. It introduces a new "smmuv3_poll" function
and replaces inline functions for accessing SMMU registers
with mmio read/write operations. Also the infinite loop
for the poll has been replaced with a counter based timeout.

Change-Id: I7a0547beb1509601f253e126b1a7a6ab3b0307e7
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>