2014-05-08 |
Merge pull request #63 from soby-mathew/sm/save_callee_saved_registers_in_cpu_context-1
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Preserve x19-x29 across world switch for exception handling
danh-arm
committed
on 8 May 2014
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Preserve x19-x29 across world switch for exception handling
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Previously exception handlers in BL3-1, X19-X29 were not saved
and restored on every SMC/trap into EL3. Instead these registers
were 'saved as needed' as a side effect of the A64 ABI used by the C
compiler.
That approach failed when world switching but was not visible
with the TSP/TSPD code because the TSP is 64-bit, did not
clobber these registers when running and did not support pre-emption
by normal world interrupts. These scenarios showed
that the values in these registers can be passed through a world
switch, which broke the normal and trusted world assumptions
about these registers being preserved.
The Ideal solution saves and restores these registers when a
world switch occurs - but that type of implementation is more complex.
So this patch always saves and restores these registers on entry and
exit of EL3.
Fixes ARM-software/tf-issues#141
Change-Id: I9a727167bbc594454e81cf78a97ca899dfb11c27
Soby Mathew
committed
on 8 May 2014
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Merge pull request #58 from athoelke/optimise-cache-flush-v2
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Optimise data cache clean/invalidate operation v2
danh-arm
committed
on 8 May 2014
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Merge pull request #61 from athoelke/use-mrs-msr-from-assembler-v2
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Use MRS/MSR instructions in assembler code v2
danh-arm
committed
on 8 May 2014
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Merge pull request #60 from athoelke/disable-mmu-v2
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Replace disable_mmu with assembler version v2
danh-arm
committed
on 8 May 2014
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Remove unused 'PL011_BASE' macro
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'PL011_BASE' macro is no longer used because the right UART base
address is now directly given to the 'console_init()' function.
This patch removes it.
Change-Id: I94759c99602df4876291a56f9f6a75de337a65ec
Sandrine Bailleux
committed
on 8 May 2014
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2014-05-07 |
Optimise data cache clean/invalidate operation
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The data cache clean and invalidate operations dcsw_op_all()
and dcsw_op_loius() were implemented to invoke a DSB and ISB
barrier for every set/way operation. This adds a substantial
performance penalty to an already expensive operation.
These functions have been reworked to provide an optimised
implementation derived from the code in section D3.4 of the
ARMv8 ARM. The helper macro setup_dcsw_op_args has been moved
and reworked alongside the implementation.
Fixes ARM-software/tf-issues#146
Change-Id: Icd5df57816a83f0a842fce935320a369f7465c7f
Andrew Thoelke
committed
on 7 May 2014
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Remove unused or invalid asm helper functions
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There are a small number of non-EL specific helper functions
which are no longer used, and also some unusable helper
functions for non-existant registers.
This change removes all of these functions.
Change-Id: Idd656cef3b59cf5c46fe2be4029d72288b649c24
Andrew Thoelke
committed
on 7 May 2014
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Access system registers directly in assembler
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Instead of using the system register helper functions to read
or write system registers, assembler coded functions should
use MRS/MSR instructions. This results in faster and more
compact code.
This change replaces all usage of the helper functions with
direct register accesses.
Change-Id: I791d5f11f257010bb3e6a72c6c5ab8779f1982b3
Andrew Thoelke
committed
on 7 May 2014
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Replace disable_mmu with assembler version
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disable_mmu() cannot work as a C function as there is no control
over data accesses generated by the compiler between disabling and
cleaning the data cache. This results in reading stale data from
main memory.
As assembler version is provided for EL3, and a variant that also
disables the instruction cache which is now used by the BL1
exception handling function.
Fixes ARM-software/tf-issues#147
Change-Id: I0cf394d2579a125a23c2f2989c2e92ace6ddb1a6
Andrew Thoelke
committed
on 7 May 2014
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2014-05-06 |
Remove variables from .data section
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Update code base to remove variables from the .data section,
mainly by using const static data where possible and adding
the const specifier as required. Most changes are to the IO
subsystem, including the framework APIs. The FVP power
management code is also affected.
Delay initialization of the global static variable,
next_image_type in bl31_main.c, until it is realy needed.
Doing this moves the variable from the .data to the .bss
section.
Also review the IO interface for inconsistencies, using
uintptr_t where possible instead of void *. Remove the
io_handle and io_dev_handle typedefs, which were
unnecessary, replacing instances with uintptr_t.
Fixes ARM-software/tf-issues#107.
Change-Id: I085a62197c82410b566e4698e5590063563ed304
Dan Handley
committed
on 6 May 2014
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Reduce deep nesting of header files
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Reduce the number of header files included from other header
files as much as possible without splitting the files. Use forward
declarations where possible. This allows removal of some unnecessary
"#ifndef __ASSEMBLY__" statements.
Also, review the .c and .S files for which header files really need
including and reorder the #include statements alphabetically.
Fixes ARM-software/tf-issues#31
Change-Id: Iec92fb976334c77453e010b60bcf56f3be72bd3e
Dan Handley
committed
on 6 May 2014
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Always use named structs in header files
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Add tag names to all unnamed structs in header files. This
allows forward declaration of structs, which is necessary to
reduce header file nesting (to be implemented in a subsequent
commit).
Also change the typedef names across the codebase to use the _t
suffix to be more conformant with the Linux coding style. The
coding style actually prefers us not to use typedefs at all but
this is considered a step too far for Trusted Firmware.
Also change the IO framework structs defintions to use typedef'd
structs to be consistent with the rest of the codebase.
Change-Id: I722b2c86fc0d92e4da3b15e5cab20373dd26786f
Dan Handley
committed
on 6 May 2014
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Move PSCI global functions out of private header
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Move the PSCI global functions out of psci_private.h and into
psci.h to allow the standard service to only depend on psci.h.
Change-Id: I8306924a3814b46e70c1dcc12524c7aefe06eed1
Dan Handley
committed
on 6 May 2014
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Separate BL functions out of arch.h
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Move the BL function prototypes out of arch.h and into the
appropriate header files to allow more efficient header file
inclusion. Create new BL private header files where there is no
sensible existing header file.
Change-Id: I45f3e10b72b5d835254a6f25a5e47cf4cfb274c3
Dan Handley
committed
on 6 May 2014
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Refactor GIC header files
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Move the function prototypes from gic.h into either gic_v2.h or
gic_v3.h as appropriate. Update the source files to include the
correct headers.
Change-Id: I368cfda175cdcbd3a68f46e2332738ec49048e19
Dan Handley
committed
on 6 May 2014
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Separate out CASSERT macro into own header
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Separate out the CASSERT macro out of bl_common.h into its own
header to allow more efficient header inclusion.
Change-Id: I291be0b6b8f9879645e839a8f0dd1ec9b3db9639
Dan Handley
committed
on 6 May 2014
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Make use of user/system includes more consistent
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Make codebase consistent in its use of #include "" syntax for
user includes and #include <> syntax for system includes.
Fixes ARM-software/tf-issues#65
Change-Id: If2f7c4885173b1fd05ac2cde5f1c8a07000c7a33
Dan Handley
committed
on 6 May 2014
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Move FVP power driver to FVP platform
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Move the FVP power driver to a directory under the FVP platform
port as this is not a generically usable driver.
Change-Id: Ibc78bd88752eb3e3964336741488349ac345f4f0
Dan Handley
committed
on 6 May 2014
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Move include and source files to logical locations
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Move almost all system include files to a logical sub-directory
under ./include. The only remaining system include directories
not under ./include are specific to the platform. Move the
corresponding source files to match the include directory
structure.
Also remove pm.h as it is no longer used.
Change-Id: Ie5ea6368ec5fad459f3e8a802ad129135527f0b3
Dan Handley
committed
on 6 May 2014
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2014-04-29 |
Preserve PSCI cpu_suspend 'power_state' parameter.
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This patch saves the 'power_state' parameter prior to suspending
a cpu and invalidates it upon its resumption. The 'affinity level'
and 'state id' fields of this parameter can be read using a set of
public and private apis. Validation of power state parameter is
introduced which checks for SBZ bits are zero.
This change also takes care of flushing the parameter from the cache
to main memory. This ensures that it is available after cpu reset
when the caches and mmu are turned off. The earlier support for
saving only the 'affinity level' field of the 'power_state' parameter
has also been reworked.
Fixes ARM-Software/tf-issues#26
Fixes ARM-Software/tf-issues#130
Change-Id: Ic007ccb5e39bf01e0b67390565d3b4be33f5960a
Vikram Kanigiri
committed
on 29 Apr 2014
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2014-04-24 |
Add TrustZone (TZC-400) driver
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The TZC-400 performs security checks on transactions to memory or
peripherals. Separate regions can be created in the address space each
with individual security settings.
Limitations:
This driver does not currently support raising an interrupt on access
violation.
Change-Id: Idf8ed64b4d8d218fc9b6f9d75acdb2cd441d2449
Harry Liebel
committed
on 24 Apr 2014
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2014-04-15 |
Allocate single stacks for BL1 and BL2
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The BL images share common stack management code which provides
one coherent and one cacheable stack for every CPU. BL1 and BL2
just execute on the primary CPU during boot and do not require
the additional CPU stacks. This patch provides separate stack
support code for UP and MP images, substantially reducing the
RAM usage for BL1 and BL2 for the FVP platform.
This patch also provides macros for declaring stacks and
calculating stack base addresses to improve consistency where
this has to be done in the firmware.
The stack allocation source files are now included via
platform.mk rather than the common BLx makefiles. This allows
each platform to select the appropriate MP/UP stack support
for each BL image.
Each platform makefile must be updated when including this
commit.
Fixes ARM-software/tf-issues#76
Change-Id: Ia251f61b8148ffa73eae3f3711f57b1ffebfa632
Andrew Thoelke
committed
on 15 Apr 2014
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Merge pull request #36 from athoelke/at/gc-sections-80
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Using GCC --gc-sections to eliminate unused code and data
danh-arm
committed
on 15 Apr 2014
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2014-04-08 |
Define frequency of system counter in platform code
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BL3-1 architecture setup code programs the system counter frequency
into the CNTFRQ_EL0 register. This frequency is defined by the
platform, though. This patch introduces a new platform hook that
the architecture setup code can call to retrieve this information.
In the ARM FVP port, this returns the first entry of the frequency
modes table from the memory mapped generic timer.
All system counter setup code has been removed from BL1 as some
platforms may not have initialized the system counters at this stage.
The platform specific settings done exclusively in BL1 have been moved
to BL3-1. In the ARM FVP port, this consists in enabling and
initializing the System level generic timer. Also, the frequency change
request in the counter control register has been set to 0 to make it
explicit it's using the base frequency. The CNTCR_FCREQ() macro has been
fixed in this context to give an entry number rather than a bitmask.
In future, when support for firmware update is implemented, there
is a case where BL1 platform specific code will need to program
the counter frequency. This should be implemented at that time.
This patch also updates the relevant documentation.
It properly fixes ARM-software/tf-issues#24
Change-Id: If95639b279f75d66ac0576c48a6614b5ccb0e84b
Sandrine Bailleux
committed
on 8 Apr 2014
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2014-04-03 |
Add missing #include guard in xlat_tables.h
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Change-Id: I7272a800accb7de71cbbf6b715a43061bbf79f8c
Sandrine Bailleux
committed
on 3 Apr 2014
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2014-03-26 |
Place assembler functions in separate sections
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This extends the --gc-sections behaviour to the many assembler
support functions in the firmware images by placing each function
into its own code section. This is achieved by creating a 'func'
macro used to declare each function label.
Fixes ARM-software/tf-issues#80
Change-Id: I301937b630add292d2dec6d2561a7fcfa6fec690
Andrew Thoelke
committed
on 26 Mar 2014
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Add standby state support in PSCI cpu_suspend api
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This patch adds support in the generic PSCI implementation to call a
platform specific function to enter a standby state using an example
implementation in ARM FVP port
Fixes ARM-software/tf-issues#94
Change-Id: Ic1263fcf25f28e09162ad29dca954125f9aa8cc9
Vikram Kanigiri
authored
on 21 Mar 2014
Dan Handley
committed
on 26 Mar 2014
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2014-03-21 |
Remove partially qualified asm helper functions
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Each ARM Trusted Firmware image should know in which EL it is running
and it should use the corresponding register directly instead of reading
currentEL and knowing which asm register to read/write
Change-Id: Ief35630190b6f07c8fbb7ba6cb20db308f002945
Vikram Kanigiri
authored
on 11 Mar 2014
Dan Handley
committed
on 21 Mar 2014
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2014-03-20 |
Rework bakery lock with WFE/SEV sequence
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Current implementation of Bakery Lock does tight-loop waiting upon lock
contention.
This commit reworks the implementation to use WFE instruction for
waiting, and SEV to signal lock availability. It also adds the rationale
for choosing Bakery Locks instead of exclusion primitives, and more
comments for the lock algorithm.
Fixes ARM-software/tf-issue#67
Change-Id: Ie351d3dbb27ec8e64dbc9507c84af07bd385a7df
Co-authored-by: Vikram Kanigiri <vikram.kanigiri@arm.com>
Jeenu Viswambharan
authored
on 13 Mar 2014
Dan Handley
committed
on 20 Mar 2014
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