tools: Set the tool's default binary name ...

This patch: fafd3ec9c assumes that tools must build from
the main makefile folder.
This assumption leads to the error when somebody wants to
build a tool from the tool's folder.
Hence changes are done to provide the default binary name
in the tool's makefile.

Change-Id: Iae570a7f8d322151376b6feb19e739300eecc3fc
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

Merge "lib: cpu: Check SCU presence in DSU before accessing DSU registers" into integration

Merge "psci: utility api to invoke stop for other cores" into integration

Merge "Add Chris Kay as code owner for CMake Build Definitions." into integration

Add Chris Kay as code owner for CMake Build Definitions. ...

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I69365d4aed1160af41e291f6e4b1dd31cbd12e02

psci: utility api to invoke stop for other cores ...

The API can be used to invoke a 'stop_func' callback for all
other cores from any initiating core. Optionally it can also
wait for other cores to power down. There may be various use
of such API by platform. Ex: Platform may use this to power
down all other cores from a crashed core.

Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
Change-Id: I4f9dc8a38d419f299c021535d5f1bcc6883106f9

Merge "spd: trusty: allow clients to retrieve service UUID" into integration

Merge "maintainers: step down as code owner of UniPhier platform" into integration

Merge "arm_fpga: Add support to populate the CPU nodes in the DTB" into integration

lib: cpu: Check SCU presence in DSU before accessing DSU registers ...

The DSU contains system control registers in the SCU and L3 logic to
control the functionality of the cluster. If "DIRECT CONNECT" L3
memory system variant is used, there won't be any L3 cache,
snoop filter, and SCU logic present hence no system control register
will be present. Hence check SCU presence before accessing DSU register
for DSU_936184 errata.

Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com>
Change-Id: I1ffa8afb0447ae3bd1032c9dd678d68021fe5a63

Merge "Tegra: common: fixup the bl31 code size to be copied at reset" into integration

arm_fpga: Add support to populate the CPU nodes in the DTB ...

At the moment BL31 dynamically discovers the CPU topology of an FPGA
system at runtime, but does not export it to the non-secure world.
Any BL33 user would typically looks at the devicetree to learn about
existing CPUs.

This patch exports a minimum /cpus node in a devicetree to satisfy
the binding. This means that no cpumaps or caches are described.
This could be added later if needed.

An existing /cpus node in the DT will make the code bail out with a
message.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I589a2b3412411a3660134bdcef3a65e8200e1d7e

Merge "Move static vars into functions in bl1" into integration

Merge "plat/arm: Get the base address of nv-counters from device tree" into integration

Merge "dtsi: Update the nv-counter node in the device tree" into integration

Merge changes from topic "tegra-downstream-08282020" into integration ...

* changes:
  Tegra: common: disable GICC after domain off
  cpus: denver: skip DCO enable/disable for recent SKUs

Merge "Remove Jack Bond-Preston as CMake Build Definitions code owner" into integration

Merge "Add support to export a /cpus node to the device tree." into integration

Add support to export a /cpus node to the device tree. ...

This patch creates and populates the /cpus node in a device tree
based on the existing topology. It uses the minimum required nodes
and properties to satisfy the binding as specified in
https://www.kernel.org/doc/Documentation/devicetree/bindings/arm/cpus.txt

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I03bf4e9a6427da0a3b8ed013f93d7bc43b5c4df0

Merge "sp_min: Avoid platform security reconfiguration" into integration

Merge "doc: Update the cot-binding for nv-counter node" into integration

Merge changes from topic "tegra-downstream-08282020" into integration ...

* changes:
  Tegra: platform specific BL31_SIZE
  Tegra186: sanity check power state type
  Tegra: fixup CNTPS_TVAL_EL1 delay timer reads
  Tegra: add platform specific 'runtime_setup' handler
  Tegra: remove ENABLE_SVE_FOR_NS = 0
  lib: cpus: denver: add MIDR PN9 variant
  cpus: denver: introduce macro to declare cpu_ops

spd: trusty: allow clients to retrieve service UUID ...

This patch implements support for the 64-bit and 32-bit versions of
0xBF00FF01 SMC function ID, as documented by the SMCCC, to allow
non-secure world clients to query SPD's UUID.

In order to service this FID, the Trusty SPD now increases the range
of SMCs that it services. To restrict Trusty from receiving the extra
SMC FIDs, this patch drops any unsupported FID.

Verified with TFTF tests for UID query and internal gtest for Trusty.

Change-Id: If96fe4993f7e641595cfe67cc6b4210a0d52403f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: common: fixup the bl31 code size to be copied at reset ...

If the CPU doesn't run from BL31_BASE, the firmware needs to be
copied from load address to BL31_BASE during cold boot. The size
should be the actual size of the code, which is indicated by the
__RELA_END__ linker variable.

This patch updates the copy routine to use this variable as a
result.

Signed-off-by: anzhou <anzhou@nvidia.com>
Change-Id: Ie3a48dd54cda1dc152204903d609da3117a0ced9

Tegra: common: disable GICC after domain off ...

The the GIC CPU interface should be disabled after cpu off. The
Tegra power management code should mark the connected core as asleep
as part of the CPU off sequence.

This patch disables the GICC after CPU off as a result.

Signed-off-by: anzhou <anzhou@nvidia.com>
Change-Id: Ib1a3d8903f5e6d55bd2ee0c16134dbe2562235ea

cpus: denver: skip DCO enable/disable for recent SKUs ...

DCO is not supported by the SKUs released after MIDR_PN4. This
patch skips enabling or disabling the DCO on these SKUs.

Change-Id: Ic31a829de3ae560314d0fb5c5e867689d4ba243b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: platform specific BL31_SIZE ...

This patch moves the BL31_SIZE to the Tegra SoC specific
tegra_def.h. This helps newer platforms configure the size of
the memory available for BL31.

Signed-off-by: anzhou <anzhou@nvidia.com>
Change-Id: I43c60b82fa7e43d5b05d87fbe7d673d729380d82

Tegra186: sanity check power state type ...

This patch sanity checks the power state type before use,
from the platform's PSCI handler.

Verified with TFTF Standard Test Suite.

Change-Id: Icd45faac6c023d4ce7f3597b698d01b91a218124
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: fixup CNTPS_TVAL_EL1 delay timer reads ...

The delay_timer driver for Tegra uses the CNTPS_TVAL_EL1 secure, physical,
decrementing timer as the source. The current logic incorrectly marks this
as an incrementing timer, by negating the timer value.

This patch fixes the anomaly and updates the driver to remove this logic.

Signed-off-by: anzhou <anzhou@nvidia.com>
Change-Id: I60490bdcaf0b66bf4553a6de3f4e4e32109017f4

Tegra: add platform specific 'runtime_setup' handler ...

Tegra SoCs would like the flexibility to perform chip specific actions
before we complete cold boot. This patch introduces a platform specific
'runtime_setup' handler to provide that flexibility.

Change-Id: I13b2489f631f775cae6f92acf51a240cd036ef11
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>