LuminaSensum/arm-trusted-firmware

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LuminaSensum / arm-trusted-firmware

2020-10-28	b6cec33 Browse files » mediatek: mt8192: add sys_cirq driver ... 1.add sys_cirq driver 2.add gic api for cirq Change-Id: Ie6802d6ddcf7dde3412a050736dfdc85f97cb51b Signed-off-by: gtk_pangao <gtk_pangao@mediatek.com> gtk_pangao authored on 19 Dec 2019 Nina Wu committed on 28 Oct 2020
2020-10-26	054af8f Browse files » mediatek: mt8192: add GPIO driver support ... add GPIO driver Change-Id: I67a9abef078e7a62b34dfbd366b45c03892800cd Signed-off-by: Po Xu <jg_poxu@mediatek.com> Po Xu committed on 26 Oct 2020
2020-10-21	bc98a2e Browse files » Merge changes from topic "tc0_sel2_spmc" into integration ... * changes: plat: tc0: Configure TZC with secure world regions plat: tc0: Enable SPMC execution at S-EL2 plat: tc0: Add TZC DRAM1 region for SPMC and trusted OS plat: arm: Make BL32_BASE platform dependent when SPD_spmd is enabled plat: tc0: Disable SPE Manish Pandey authored on 21 Oct 2020 TrustedFirmware Code Review committed on 21 Oct 2020
2020-10-21	c4d919e Browse files » Merge changes from topic "tc0_sel2_spmc" into integration ... * changes: lib: el3_runtime: Fix SPE system registers in el2_sysregs_context lib: el3_runtime: Conditionally save/restore EL2 NEVE registers lib: el3_runtime: Fix aarch32 system registers in el2_sysregs_context Manish Pandey authored on 21 Oct 2020 TrustedFirmware Code Review committed on 21 Oct 2020
2020-10-20	bd260fc Browse files » Merge "docs: code review guidelines" into integration Manish Pandey authored on 20 Oct 2020 TrustedFirmware Code Review committed on 20 Oct 2020
	879b5b8 Browse files » plat: tc0: Configure TZC with secure world regions ... This includes configuration for SPMC and trusted OS. Change-Id: Ie24df200f446b3f5b23f5f764b115c7191e6ada3 Signed-off-by: Usama Arif <usama.arif@arm.com> Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Usama Arif authored on 26 Aug 2020 Manish Pandey committed on 20 Oct 2020
	b0d1275 Browse files » plat: tc0: Enable SPMC execution at S-EL2 ... This patch enables SPMC execution at S-EL2 by adding below changes - Map TC0_MAP_TZC_DRAM1 for loading SPMC - Add details of cactus test secure partitions - Adds tc0 spmc manifest file with details on secure partitions - Inlcude TOS_FW_CONFIG when SPM is spmd - Increases bl2 image size SPMC at S-EL2 is only enabled when build with SPD=spmd. Change-Id: I4c5f70911903c232ee8ecca57f1e288d6b1cd647 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Arunachalam Ganapathy authored on 22 Sep 2020 Manish Pandey committed on 20 Oct 2020
	a3ecbb3 Browse files » plat: tc0: Add TZC DRAM1 region for SPMC and trusted OS ... - Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for TC0_TZC_DRAM1 - Add TC0_NS_DRAM1 base and mapping - Reserve memory region in tc0.dts Change-Id: If2431f7f68e4255e28c86a0e89637dab7c424a13 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Arunachalam Ganapathy authored on 22 Sep 2020 Manish Pandey committed on 20 Oct 2020
	d32113c Browse files » plat: arm: Make BL32_BASE platform dependent when SPD_spmd is enabled ... To support platforms without Trusted DRAM this patch defines PLAT_ARM_SPMC_BASE and enables platform to use either Trusted DRAM or DRAM region behind TZC. Change-Id: Icaa5c7d33334258ff27e8e0bfd0812c304e68ae4 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Arunachalam Ganapathy authored on 27 Jul 2020 Manish Pandey committed on 20 Oct 2020
	c398caf Browse files » plat: tc0: Disable SPE ... Statistical Profiling Extension is not supported by Matterhorn core Change-Id: Iec652f1c6d6b6a9bf118ba682276a7c70a6abc0d Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Arunachalam Ganapathy authored on 28 May 2020 Manish Pandey committed on 20 Oct 2020
	2b036b7 Browse files » lib: el3_runtime: Fix SPE system registers in el2_sysregs_context ... Include EL2 registers related to SPE in EL2 context save/restore routines if architecture supports it and platform wants to use these features in Secure world. Change-Id: Ie01a2c38fa5f6c907276eddec120fdfb222561a6 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Arunachalam Ganapathy authored on 9 Oct 2020 Manish Pandey committed on 20 Oct 2020
	062f8aa Browse files » lib: el3_runtime: Conditionally save/restore EL2 NEVE registers ... Include EL2 registers related to Nested Virtualization in EL2 context save/restore routines if architecture supports it and platform wants to use these features in Secure world. Change-Id: If006ab83bbc2576488686f5ffdff88b91adced5c Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Arunachalam Ganapathy authored on 28 May 2020 Manish Pandey committed on 20 Oct 2020
	0f777ea Browse files » lib: el3_runtime: Fix aarch32 system registers in el2_sysregs_context ... AArch64-only platforms do not implement AArch32 at EL1 and higher ELs. In such cases the build option CTX_INCLUDE_AARCH32_REGS is set to 0. So don't save/restore aarch32 system registers in el2_sysregs_context save/restore routines if CTX_INCLUDE_AARCH32_REGS is set to 0. Change-Id: I229cdd46136c4b4bc9623b02eb444d904e09ce5a Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Arunachalam Ganapathy authored on 26 May 2020 Manish Pandey committed on 20 Oct 2020
2020-10-19	3226949 Browse files » Merge "fdts: add missing hash node in STM32MP157C-ED1 board DT" into integration Alexei Fedorov authored on 19 Oct 2020 TrustedFirmware Code Review committed on 19 Oct 2020
2020-10-18	943aff0 Browse files » Merge "Increase type widths to satisfy width requirements" into integration Joanna Farley authored on 18 Oct 2020 TrustedFirmware Code Review committed on 18 Oct 2020
2020-10-16	4a6b33e Browse files » Merge changes Iba51bff1,I3f563cff into integration ... * changes: plat:qti Mandate SMC implementaion and bug fix Update in coreboot_get_memory_type API to include size as well Madhukar Pappireddy authored on 16 Oct 2020 TrustedFirmware Code Review committed on 16 Oct 2020
	2973603 Browse files » Merge "docs: Remove deprecated information" into integration Mark Dykes authored on 16 Oct 2020 TrustedFirmware Code Review committed on 16 Oct 2020
	2cad7df Browse files » Merge "docs: Update Release information for v2.5" into integration Mark Dykes authored on 16 Oct 2020 TrustedFirmware Code Review committed on 16 Oct 2020
	1fa9b27 Browse files » Merge "docs: Update code freeze and release target date for v2.4" into integration Mark Dykes authored on 16 Oct 2020 TrustedFirmware Code Review committed on 16 Oct 2020
	3bd1957 Browse files » docs: Remove deprecated information ... There are no references to AARCH32, AARCH64 and __ASSEMBLY__ macros in the TF-A code hence removed the deprecated information mentioning about these macros in the document. Change-Id: I472ab985ca2e4173bae23ff7b4465a9b60bc82eb Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Manish V Badarkhe authored on 7 Oct 2020 Manish V Badarkhe committed on 16 Oct 2020
	c20bbfa Browse files » docs: Update Release information for v2.5 ... Updated tentative code freeze and release target date for v2.5 release. Change-Id: Idcfd9a127e9210846370dfa0685badac5b1c25c7 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Manish V Badarkhe authored on 7 Oct 2020 Manish V Badarkhe committed on 16 Oct 2020
	f329442 Browse files » docs: Update code freeze and release target date for v2.4 ... Updated code freeze and release information date for v2.4 release. Change-Id: I76d5d04d0ee062a350f6a693eb04c29017d8b2e0 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Manish V Badarkhe authored on 7 Oct 2020 Manish V Badarkhe committed on 16 Oct 2020
2020-10-15	3bddca4 Browse files » Merge changes I0005959b,I2ea59edb into integration ... * changes: bl32: add an assert on BL32_SIZE in sp_min.ld.S bl32: use SORT_BY_ALIGNMENT macro in sp_min.ld.S Manish Pandey authored on 15 Oct 2020 TrustedFirmware Code Review committed on 15 Oct 2020
	4b91845 Browse files » plat:qti Mandate SMC implementaion and bug fix ... implementation of SMC call SMCCC_ARCH_SOC_ID adding debugging logs in mem assign call. Checking range of param in mem_assign call is from CB_MEM_RAM or CB_MEM_RESERVED. Change-Id: Iba51bff154df01e02dcb7715582ffaff7beba26e Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org> Saurabh Gorecha committed on 15 Oct 2020
	e0caf8f Browse files » Update in coreboot_get_memory_type API to include size as well ... Change-Id: I3f563cffd58b0591b433c85c0ff6b71e486eb2c8 Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org> Saurabh Gorecha committed on 15 Oct 2020
2020-10-14	dfe577a Browse files » Merge "Don't return error information from console_flush" into integration Mark Dykes authored on 14 Oct 2020 TrustedFirmware Code Review committed on 14 Oct 2020
2020-10-14	5dfe680 Browse files » Merge "stm32mp1: use %u in NOTICE message for board info" into integration Alexei Fedorov authored on 14 Oct 2020 TrustedFirmware Code Review committed on 14 Oct 2020
2020-10-13	b37b52e Browse files » fdts: add missing hash node in STM32MP157C-ED1 board DT ... Without this node, the board fails to boot and panics in the function stm32mp_init_auth(). Change-Id: Ia54924410dac2a8c94dd6e45d7e93977fe7d87e2 Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier committed on 13 Oct 2020
	ab049ec Browse files » stm32mp1: use %u in NOTICE message for board info ... The board information values, read in an OTP are never negative, %u is then used instead of %d. Change-Id: I3bc22401fb4d54666ddf56411f75b79aca738492 Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier committed on 13 Oct 2020
	80d9cf7 Browse files » Merge changes from topic "stm32mp1_plat_updates" into integration ... * changes: docs: update STM32MP1 with versions details stm32mp1: get peripheral base address from a define stm32mp1: add finished good variant in board identifier Madhukar Pappireddy authored on 13 Oct 2020 TrustedFirmware Code Review committed on 13 Oct 2020