spmd: skip loading of secure partitions on pre-v8.4 platforms ...

When SPD=spmd and SPMD_SPM_AT_SEL2=0, that is SPMC sits at S-EL1
then there is no need for TF-A to load secure partitions individually.
In this configuration, SPMC handles secure partition loading at
S-EL1/EL0 levels.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I06a0d88a4811274a8c347ce57b56bb5f64e345df

Merge changes from topic "rpix-multi-console" into integration ...

* changes:
  rpi: docs: Update maintainers file to new RPi directory scheme
  rpi: console: Autodetect Mini-UART vs. PL011 configuration
  rpi3: build: Include GPIO driver in all BL stages
  rpi: Allow using PL011 UART for RPi3/RPi4
  rpi3: console: Use same "clock-less" setup scheme as RPi4
  rpi3: gpio: Simplify GPIO setup

Merge "Implement SMCCC_ARCH_SOC_ID SMC call" into integration

Merge "FVP: In BL31/SP_MIN, map only the needed DRAM region statically" into integration

Merge "board/rddaniel: add NSAID sources for TZC400 driver" into integration

FVP: In BL31/SP_MIN, map only the needed DRAM region statically ...

Rather than creating entry in plat_arm_mmap array to map the
entire DRAM region in BL31/SP_MIN, only map a smaller region holding
HW_CONFIG DTB. Consequently, an increase in number of sub-translation
tables(level-2 and level-3) i.e., MAX_XLAT_TABLES is necessary to map
the new region in memory.

In order to accommodate the increased code size in BL31 i.e.,
PROGBITS, the max size of BL31 image is increased by 0x1000(4K).

Change-Id: I540b8ee550588e22a3a9fb218183d2ab8061c851
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

rpi: docs: Update maintainers file to new RPi directory scheme ...

With the addition of the Raspberry Pi 4 port the directory structure
changed a bit, also the new port didn't have a separate entry.

Add a new entry for the RPi4 port and adjust the path names.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I04b60e729a19bb0cc3dd6ce6899ec6480356b1f1

rpi: console: Autodetect Mini-UART vs. PL011 configuration ...

The Raspberry Pi has two different UART devices pin-muxed to GPIO 14&15:
One ARM PL011 one and the 8250 compatible "Mini-UART".
A dtoverlay parameter in config.txt will tell the firmware to switch
between the two: it will setup the right clocks and will configure the
pinmuxes accordingly.

To autodetect the user's choice, we read the pinmux register and check
its setting: ALT5 (0x2) means the Mini-UART is used, ALT0 (0x4) points
to the PL011.
Based on that we select the UART driver to initialise.

This will allow console output in any case.

Change-Id: I620d3ce68de6c6576599f2a405636020e1fd1376
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

rpi3: build: Include GPIO driver in all BL stages ...

So far the Raspberry Pi 3 build needs the GPIO driver just for BL2.
Upcoming changes will require some GPIO code in BL1 and BL31 also, so
move those driver files into the common source section.

This does not affect BL31 code size at all, and bl1.bin just increases
by 144 bytes, but doesn't affect the padded binary size at all.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I7639746dc241c1e69099d85d2671c65fa0108555

rpi: Allow using PL011 UART for RPi3/RPi4 ...

The Broadcom 283x SoCs feature multiple UARTs: the mostly used
"Mini-UART", which is an 8250 compatible IP, and at least one PL011.
While the 8250 is usually used for serial console purposes, it suffers
from a design flaw, where its clock depends on the VPU clock, which can
change at runtime. This will reliably mess up the baud rate.
To avoid this problem, people might choose to use the PL011 UART for
the serial console, which is pin-mux'ed to the very same GPIO pins.
This can be done by adding "miniuart-bt" to the "dtoverlay=" line in
config.txt.

To prepare for this situation, use the newly gained freedom of sharing
one console_t pointer across different UART drivers, to introduce the
option of choosing the PL011 for the console.

This is for now hard-coded to choose the Mini-UART by default.
A follow-up patch will introduce automatic detection.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I8cf2522151e09ff4ff94a6d396aec6fc4b091a05

rpi3: console: Use same "clock-less" setup scheme as RPi4 ...

In the wake of the upcoming unification of the console setup code
between RPi3 and RPi4, extend the "clock-less" setup scheme to the
RPi3. This avoid programming any clocks or baud rate registers,
which makes the port more robust against GPU firmware changes.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ida83a963bb18a878997e9cbd55f8ceac6a2e1c1f

rpi3: gpio: Simplify GPIO setup ...

There is really no reason to use and pass around a struct when its only
member is the (fixed) base address.

Remove the struct and just use the base address on its own inside the
GPIO driver. Then set the base address automatically.

This simplifies GPIO setup for users, which now don't need to deal with
zeroing a struct and setting the base address anymore.

Change-Id: I3060f7859e3f8ef9a24cc8fb38307b5da943f127
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Implement SMCCC_ARCH_SOC_ID SMC call ...

Implemented SMCCC_ARCH_SOC_ID call in order to get below
SOC information:

1. SOC revision
2. SOC version

Implementation done using below SMCCC specification document:
https://developer.arm.com/docs/den0028/c

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ie0595f1c345a6429a6fb4a7f05534a0ca9c9a48b

Merge "fconf: Add namespace guidance inside documentation" into integration

Merge "SPMD: Add support for SPCI_ID_GET" into integration

Merge "Add a .gitreview file for convenience" into integration

Merge "juno/sgm: Maximize space allocated to SCP_BL2" into integration

Merge "Mention COT build option in trusted-board-boot-build.rst" into integration

Merge "Update cryptographic algorithms in TBBR doc" into integration

SPMD: Add support for SPCI_ID_GET ...

This patch introduces the `SPCI_ID_GET` interface which will return the
ID of the calling SPCI component. Returns 0 for requests from the
non-secure world and the SPCI component ID as specified in the manifest
for secure world requests.

Change-Id: Icf81eb1d0e1d7d5c521571e04972b6e2d356e0d1
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>

Mention COT build option in trusted-board-boot-build.rst ...

Since commit 3bff910 ("Introduce COT
build option"), it is now possible to select a different Chain of Trust
than the TBBR-Client one.

Make a few adjustments in the documentation to reflect that. Also make
some minor improvements (fixing typos, better formatting, ...)  along
the way.

Change-Id: I3bbadc441557e1e13311b6fd053fdab6b10b1ba2
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Update cryptographic algorithms in TBBR doc ...

The TBBR documentation has been written along with an early
implementation of the code. At that time, the range of supported
encryption and hash algorithms was failry limited. Since then, support
for other algorithms has been added in TF-A but the documentation has
not been updated.

Instead of listing them all, which would clutter this document while
still leaving it at risk of going stale in the future, remove specific
references to the original algorithms and point the reader at the
relevant comprehensive document for further details.

Change-Id: I29dc50bc1d53b728091a1fbaa1c3970fb999f7d5
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Merge changes from topic "mp/enhanced_pal_hw" into integration ...

* changes:
  plat/arm/fvp: populate pwr domain descriptor dynamically
  fconf: Extract topology node properties from HW_CONFIG dtb
  fconf: necessary modifications to support fconf in BL31 & SP_MIN
  fconf: enhancements to firmware configuration framework

juno/sgm: Maximize space allocated to SCP_BL2 ...

To accommodate the increasing size of the SCP_BL2 binary, the base
address of the memory region allocated to SCP_BL2 has been moved
downwards from its current (mostly) arbitrary address to the beginning
of the non-shared trusted SRAM.

Change-Id: I086a3765bf3ea88f45525223d765dc0dbad6b434
Signed-off-by: Chris Kay <chris.kay@arm.com>

Merge "Use Speculation Barrier instruction for v8.5 cores" into integration

Merge "locks: bakery: add a DMB to the 'read_cache_op' macro" into integration

board/rddaniel: add NSAID sources for TZC400 driver ...

Add CLCD, HDLCD, PCI and VIRTIO devices as source interfaces for TZC
filter unit to enable DMA for these devices.

Change-Id: Ifad2e56b18605311936e03cfcccda573cac7e60a
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

Merge "n1sdp: Enable the NEOVERSE_N1_EXTERNAL_LLC flag" into integration

Merge "Changelog: Add dualroot CoT entries" into integration

Merge changes from topic "tegra-downstream-03102020" into integration ...

* changes:
  Tegra210: Remove "unsupported func ID" error msg
  Tegra210: support for secure physical timer
  spd: tlkd: secure timer interrupt handler
  Tegra: smmu: export handlers to read/write SMMU registers
  Tegra: smmu: remove context save sequence
  Tegra: bpmp: fixup TEGRA_CLK_SE values for Tegra186/Tegra194
  Tegra194: memctrl: lock some more MC SID security configs
  Tegra194: add SE support to generate SHA256 of TZRAM
  Tegra194: store TZDRAM base/size to scratch registers
  Tegra194: fix warnings for extra parentheses