rockchip: bring TZRAM_SIZE values in line ...

The agreed upon division of early boot locations is 0x40000 for bl31
to leave enough room for u-boot-spl and 0x100000 for bl33 (u-boot).

rk3288 and rk3399 already correctly secure the ddr up to the 1MB boundary
so pull the other platforms along to also give the Rockchip TF-A enough
room to comfortably live in.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: Ie9e0c927d3074a418b6fd23b599d2ed7c15c8c6f

Merge "libc: Fix SIZE_MAX on AArch32" into integration

libc: Fix SIZE_MAX on AArch32 ...

SIZE_MAX was mistakenly redefined from UINT32_MAX to UINT64_MAX
on AArch32 when the arch-specific headers were merged.

This value is not currently used by upstream TF-A source code,
so no functionality should be affected.

Change-Id: I2acf7f8736423697c7377e8ed4b08843ced26e66
Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com>

Merge "rockchip: Prevent macro expansion in paths" into integration

Merge "cryptocell: add cryptocell 712 RSA 3K support" into integration

Merge "Remove -Wpadded warning" into integration

Remove -Wpadded warning ...

-Wpadded warns whenever the C compiler automatically includes any
padding in a structure. Because TF-A has a large number of structures,
this occurs fairly frequently and is incredibly verbose, and as such is
unlikely to ever be fixed.

The utility of this warning is also extremely limited - knowing that a
structure includes padding does not point to the existence of an error,
and is probably quite unlikely to indicate actually buggy behaviour.
Therefore, it's probably best to keep this warning off at all times.

Change-Id: I0797cb75f06b4fea0d2fdc16fd5ad978a31d76ec
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>

Merge "Remove -Wmissing-declarations warning from WARNING1 level" into integration

rockchip: Prevent macro expansion in paths ...

Instead of stringizing the paths to binary files, add them as string
defines on the command line (e.g. -DFOO=\"BAR\" instead of -DFOO=BAR).
This prevents macros from being expanded inside the string value itself.
For example, -DFOO=/path/with-linux-in-it would have been expanded to
"/path/with-1-in-it" because `linux=1` is one of the standard GCC
defines.

Change-Id: I7b65df3c9930faed4f1aff75ad726982ae3671e6
Signed-off-by: Joshua Watt <JPEWhacker@gmail.com>

Merge "allwinner: Fix incorrect ARISC code patch offset check" into integration

Merge changes from topic "aa/sel2_support" into integration ...

* changes:
  S-EL2 Support: Check for AArch64
  Add support for enabling S-EL2

Merge "allwinner: power: Add DLDO4 power rail" into integration

Merge "intel: s10: Remove unused source code" into integration

Remove -Wmissing-declarations warning from WARNING1 level ...

A function declaration declares the name of the function and the type of
the parameter it returns. A function prototype is a function declaration
that also specifies the type of the arguments of the function. Essentially,
a function prototype helps the compiler ensure whether the function call
matches the return type and the right number/type of arguments of function.
A function prototype itself serves as a function declaration for new style
functions.
The warning flag -wmissing-prototype is good enough to check for missing
function prototype and is exhaustive compared to -wmissing-declaration,
therefore  making the later redundant.

Note that, at this point, these flags are part of WARNING1 which is not
used for TF-A build by default. Several platforms use upstream libraries
(such as zlib etc) which are in old style c code. After the TF-A build
process is restructred using CMake framework, we plan to enable WARNING1,
WARNING2 and WARNING3 incrementally as the new build platform can compile
each BL binary of a particular platform with set of  unique compilation
flags.

Change-Id: I9c6bf9da74e0840e4d2624bc12376e199953c213
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>

Merge changes from topic "enable-tegra194-compilation" into integration ...

* changes:
  docs: tegra: add support for Tegra194 class of SoCs
  Tegra194: smmu: add support for backup multiple smmu regs
  Tegra194: introduce tegra_mc_def.h
  Tegra194: 40-bit wide memory address space
  Tegra194: psci: rename 'percpu_data' variable

Merge "PIE: make call to GDT relocation fixup generalized" into integration

PIE: make call to GDT relocation fixup generalized ...

When a Firmware is complied as Position Independent Executable it needs
to request GDT fixup by passing size of the memory region to
el3_entrypoint_common macro.
The Global descriptor table fixup will be done early on during cold boot
process of primary core.

Currently only BL31 supports PIE, but in future when BL2_AT_EL3 will be
compiled as PIE, it can simply pass fixup size to the common el3
entrypoint macro to fixup GDT.

The reason for this patch was to overcome the bug introduced by SHA
330ead806 which called fixup routine for each core causing
re-initializing of global pointers thus overwriting any changes
done by the previous core.

Change-Id: I55c792cc3ea9e7eef34c2e4653afd04572c4f055
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

intel: s10: Remove unused source code ...

remove plat_sip_svc.c and plat_psci.c in stratix 10 platform directory
as both has been refactored to common directory for sharing with agilex
platform

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I395fed66408f536e8fefd637681e742c63621818

cryptocell: add cryptocell 712 RSA 3K support ...

Add the support needed to enable using CryptoCell integration with
with RSA 3K support.

Signed-off-by: Gilad Ben-Yossef <gilad.benyossef@arm.com>
Change-Id: I95527cb0c41ae012109e8968dd20a4ae9fe67f17

Merge "libc: add memrchr" into integration

libc: add memrchr ...

This function scans a string backwards from the end for the first
instance of a character.

Change-Id: I46b21573ed25a0ff222eac340e1e1fb93b040763
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

docs: tegra: add support for Tegra194 class of SoCs ...

This patch adds the Tegra194 SoC information to the nvidia-tegra.rst
file.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Id649a5ff1b3f70eeee34b508edb7965e7b7a2454

Tegra194: smmu: add support for backup multiple smmu regs ...

Tegra194 supports multiple SMMU blocks. This patch adds support to
save register values for SMMU0 and SMMU2, before entering the System
Suspend state.

Change-Id: I3a376cdb606ea057ad7047714717245f9dced5cf
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

Tegra194: introduce tegra_mc_def.h ...

This patch introduces memory controller register defines
for Tegra194 platforms.

Change-Id: I6596341ae817b6cec30cb74d201ad854a0c8c0a6
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

Tegra194: 40-bit wide memory address space ...

This patch updates the memory address space, physical and virtual,
to be 40-bits wide for all Tegra194 platforms.

Change-Id: Ie1bcdec2c4e8e15975048ce1c2a31c2ae0dd494c
Signed-off-by: Steven Kao <skao@nvidia.com>

Tegra194: psci: rename 'percpu_data' variable ...

The per CPU wake times are saved in an array called 't19x_percpu_data'. But,
there is one instance in the code where the name of the variable is misspelt.

This patch fixes this typographical error to fix compilation errors.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I52f5f0b150c51d8cc38372675415dec7944a7735

Merge "adding support to enable different personality of the same soc." into integration

Merge "Use the proper size for tb_fw_cfg_dtb" into integration

Merge "arm: Fix current RECLAIM_INIT_CODE behavior" into integration

arm: Fix current RECLAIM_INIT_CODE behavior ...

Previously the .init section was created even when the reclaim flag was
manually set to 0.

Change-Id: Ia9e7c7997261f54a4eca725d7ea605192f60bcf8
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
	       Zelalem Aweke <zelalem.aweke@arm.com>