| 2015-08-04 |
Merge pull request #351 from davwan01/davwan01/docs-update
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Some minor fixes to interrupt-framework-design.md
danh-arm
committed
on 4 Aug 2015
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Merge pull request #349 from jcastillo-arm/jc/tbb_cert_opt
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TBB: rework cert_create tool to follow a data driven approach
danh-arm
committed
on 4 Aug 2015
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Merge pull request #348 from vwadekar/bootargs-tzdram-base-v2
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Bootargs tzdram base v2
danh-arm
committed
on 4 Aug 2015
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Some minor fixes to interrupt-framework-design.md
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This patch fixes a pair of typos. The security state had been described
as non-secure where it should have been secure.
Change-Id: Ib3f424708a6b8e2084e5447f8507ea4e9c99ee79
David Wang
committed
on 4 Aug 2015
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| 2015-08-01 |
docs: fix the command to compile BL31 on Tegra
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This patch fixes the command line used to compile BL31 on
Tegra platforms.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 1 Aug 2015
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| 2015-07-31 |
Tegra132: set TZDRAM_BASE to 0xF5C00000
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The TZDRAM base on the reference platform has been bumped up due to
some BL2 memory cleanup. Platforms can also use a different TZDRAM
base by setting TZDRAM_BASE=<value> in the build command line.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 31 Jul 2015
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Tegra: retrieve BL32's bootargs from bl32_ep_info
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This patch removes the bootargs pointer from the platform params
structure. Instead the bootargs are passed by the BL2 in the
bl32_ep_info struct which is a part of the EL3 params struct.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 31 Jul 2015
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| 2015-07-28 |
Merge pull request #344 from vwadekar/tegra-mselect-restore-v2
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Tegra210: enable WRAP to INCR burst type conversions
danh-arm
committed
on 28 Jul 2015
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| 2015-07-27 |
Tegra210: enable WRAP to INCR burst type conversions
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The Memory Select Switch Controller routes any CPU transactions to
the appropriate slave depending on the transaction address. During
system suspend, it loses all config settings and hence the CPU has
to restore them during resume.
This patch restores the controller's settings for enabling WRAP to
INCR burst type conversions on the master ports, for any incoming
requests from the AXI slave ports.
Tested by performing multiple system suspend cycles.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 27 Jul 2015
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| 2015-07-24 |
Merge pull request #342 from vwadekar/tlkd-delete-need-bl32-v1
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tlkd: delete 'NEED_BL32' build variable
danh-arm
committed
on 24 Jul 2015
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tlkd: delete 'NEED_BL32' build variable
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Remove the 'NEED_BL32' flag from the makefile. TLK compiles using a
completely different build system and is present on the device as a
binary blob. The NEED_BL32 flag does not influence the TLK load/boot
sequence at all. Moreover, it expects that TLK binary be present on
the host before we can compile BL31 support for Tegra.
This patch removes the flag from the makefile and thus decouples both
the build systems.
Tested by booting TLK without the NEED_BL32 flag.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 24 Jul 2015
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Merge pull request #341 from vwadekar/tegra-denver-plat-support-v3
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Tegra denver plat support v3
danh-arm
committed
on 24 Jul 2015
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| 2015-07-23 |
Tegra: modify 'BUILD_PLAT' to point to soc specific build dirs
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This patch modifies the 'BUILD_PLAT' makefile variable to point to the soc
specific build directory in order to allow each Tegra soc to have its own
build directory. This way we can keep the build outputs separate and can
keep multiple soc specific builds alive at the same time.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 23 Jul 2015
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Tegra: Support for Tegra's T132 platforms
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This patch implements support for T132 (Denver CPU) based Tegra
platforms.
The following features have been added:
* SiP calls to switch T132 CPU's AARCH mode
* Complete PSCI support, including 'System Suspend'
* Platform specific MMIO settings
* Locking of CPU vector registers
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 23 Jul 2015
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Add "Project Denver" CPU support
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Denver is NVIDIA's own custom-designed, 64-bit, dual-core CPU which is
fully ARMv8 architecture compatible. Each of the two Denver cores
implements a 7-way superscalar microarchitecture (up to 7 concurrent
micro-ops can be executed per clock), and includes a 128KB 4-way L1
instruction cache, a 64KB 4-way L1 data cache, and a 2MB 16-way L2
cache, which services both cores.
Denver implements an innovative process called Dynamic Code Optimization,
which optimizes frequently used software routines at runtime into dense,
highly tuned microcode-equivalent routines. These are stored in a
dedicated, 128MB main-memory-based optimization cache. After being read
into the instruction cache, the optimized micro-ops are executed,
re-fetched and executed from the instruction cache as long as needed and
capacity allows.
Effectively, this reduces the need to re-optimize the software routines.
Instead of using hardware to extract the instruction-level parallelism
(ILP) inherent in the code, Denver extracts the ILP once via software
techniques, and then executes those routines repeatedly, thus amortizing
the cost of ILP extraction over the many execution instances.
Denver also features new low latency power-state transitions, in addition
to extensive power-gating and dynamic voltage and clock scaling based on
workloads.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 23 Jul 2015
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Tegra: implement per-SoC validate_power_state() handler
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The validate_power_state() handler checks the power_state for a valid afflvl
and state id. Although the afflvl check is common, the state ids are implementation
defined.
This patch moves the handler to the tegra/soc folder to allow each SoC to validate
the power_state for supported parameters.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 23 Jul 2015
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Tegra: T210: include CPU files from SoC's platform.mk
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This patch moves the inclusion of CPU code (A53, A57) to T210's
makefile. This way we can reduce code size for Tegra platforms by
including only the required CPU files.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 23 Jul 2015
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| 2015-07-17 |
Merge pull request #337 from vwadekar/tegra-misc-fixes-v3
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Tegra misc fixes v3
danh-arm
committed
on 17 Jul 2015
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Tegra: Introduce config for enabling NS access to L2/CPUECTRL regs
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A new config, ENABLE_NS_L2_CPUECTRL_RW_ACCESS, allows Tegra platforms to
enable read/write access to the L2 and CPUECTRL registers. T210 is the
only platform that needs to enable this config for now.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 17 Jul 2015
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Tegra210: lock PMC registers holding CPU vector addresses
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This patch locks access to the PMC registers which hold the CPU reset
vector addresses. The PMC registers are used by the warmboot code and
must be locked during boot/resume to avoid booting into custom firmware
installed by unknown parties e.g. hackers.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 17 Jul 2015
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Tegra: PMC: lock SCRATCH22 register
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The PMC Scratch22 register contains the CPU reset vector to
be used by the warmboot code to power up the CPU while resuming
from system suspend. This patch locks this PMC register to avoid
any further writes.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 17 Jul 2015
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Tegra: PMC: check if a CPU is already online
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This patch checks if the target CPU is already online before
proceeding with it's power ON sequence.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 17 Jul 2015
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Tegra210: deassert CPU reset signals during power on
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This patch de-asserts the CPU reset signals for each CPU as
part of it's power on sequence. This is needed to get rid of
the wait in BPMP firmware during SC7 exit.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 17 Jul 2015
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Tegra: Fix the delay loop used during SC7 exit
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This patch fixes the delay loop used to wake up the BPMP during SC7 exit.
The earlier loop would fail just when the timer was about to wrap-around
(e.g. when TEGRA_TMRUS_BASE is 0xfffffffe, the target value becomes 0,
which would cause the loop to exit before it's expiry).
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 17 Jul 2015
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Tegra: introduce delay timer support
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This patch introduces the backend required for implementing the delay
timer API. Tegra has an on-chip free flowing us timer which can be
used as the delay timer.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 17 Jul 2015
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Merge pull request #336 from danh-arm/sb/move-user-guide-to-linaro-release
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Update user guide to use Linaro releases
danh-arm
committed
on 17 Jul 2015
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Merge pull request #335 from jcastillo-arm/jc/sh_write
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Fix bug in semihosting write function
danh-arm
committed
on 17 Jul 2015
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Merge pull request #332 from jcastillo-arm/jc/tf-issues/214
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Use uintptr_t as base address type in ARM driver APIs
danh-arm
committed
on 17 Jul 2015
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Tegra: Exclude coherent memory region from memory map
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This patch sets the 'USE_COHERENT_MEM' flag to '0', so that the
coherent memory region will not be included in the memory map.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 17 Jul 2015
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| 2015-07-16 |
Fix bug in semihosting write function
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The return value from the SYS_WRITE semihosting operation is 0 if
the call is successful or the number of bytes not written, if there
is an error. The implementation of the write function in the
semihosting driver treats the return value as the number of bytes
written, which is wrong. This patch fixes it.
Change-Id: Id39dac3d17b5eac557408b8995abe90924c85b85
Juan Castillo
authored
on 7 Jul 2015
Achin Gupta
committed
on 16 Jul 2015
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