SDEI: Make dispatches synchronous ...

SDEI event dispatches currently only sets up the Non-secure context
before returning to the caller. The actual dispatch only happens upon
exiting EL3 next time.

However, for various error handling scenarios, it's beneficial to have
the dispatch happen synchronously. I.e. when receiving SDEI interrupt,
or for a successful sdei_dispatch_event() call, the event handler is
executed; and upon the event completion, dispatcher execution resumes
after the point of dispatch. The jump primitives introduced in the
earlier patch facilitates this feature.

With this patch:

  - SDEI interrupts and calls to sdei_dispatch_event prepares the NS
    context for event dispatch, then sets a jump point, and immediately
    exits EL3. This results in the client handler executing in
    Non-secure.

  - When the SDEI client completes the dispatched event, the SDEI
    dispatcher does a longjmp to the jump pointer created earlier. For
    the caller of the sdei_dispatch_event() in particular, this would
    appear as if call returned successfully.

The dynamic workaround for CVE_2018_3639 is slightly shifted around as
part of related minor refactoring. It doesn't affect the workaround
functionality.

Documentation updated.

NOTE: This breaks the semantics of the explicit dispatch API, and any
exiting usages should be carefully reviewed.

Change-Id: Ib9c876d27ea2af7fb22de49832e55a0da83da3f9
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

BL31: Introduce jump primitives ...

This patch introduces setjmp() and ongjmp() primitives to enable
standard setjmp/longjmp style execution. Both APIs parameters take a
pointer to struct jmpbuf type, which hosts CPU registers saved/restored
during jump.

As per the standard usage:

  - setjmp() return 0 when a jump is setup; and a non-zero value when
    returning from jump.

  - The caller of setjmp() must not return, or otherwise update stack
    pointer since.

Change-Id: I4af1d32e490cfa547979631b762b4cba188d0551
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

SDEI: Determine client EL from NS context's SCR_EL3 ...

Currently, the dispatcher reads from SCR_EL3 register directly to
determine the EL of SDEI client. This is with the assumption that
SCR_EL3 is not modified throughout. However, with RAS work flows, it's
possible that SCR_EL3 register contains values corresponding to Secure
world, and therefore EL determination can go wrong. To mitigate this,
always read the register from the saved Non-secure context.

Change-Id: Ic85e4021deb18eb58757f676f9a001174998543a
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

SDEI: Allow platforms to define explicit events ...

The current macros only allow to define dynamic and statically-bound
SDEI events. However, there ought be a mechanism to define SDEI events
that are explicitly dispatched; i.e., events that are dispatched as a
result of a previous secure interrupt or other exception

This patch introduces SDEI_EXPLICIT_EVENT() macro to define an explicit
event. They must be placed under private mappings. Only the priority
flags are allowed to be additionally specified.

Documentation updated.

Change-Id: I2e12f5571381195d6234c9dfbd5904608ad41db3
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

Merge pull request #1439 from dp-arm/dp/bl2_size ...

fvp: Increase BL2 size for TBBR builds

fvp: Increase BL2 size for TBBR builds ...

Change-Id: I67e64bb79cc984ea3263f069e22738a42321c46d
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

Merge pull request #1428 from jeenu-arm/mbedtls ...

Move to mbedtls-2.10.0 tag

Merge pull request #1434 from soby-mathew/sm/fix_cntfrq ...

ARM Platforms: Update CNTFRQ register in CNTCTLBase frame

Merge pull request #1435 from antonio-nino-diaz-arm/an/xlat-fix ...

xlat_v2: Fix descriptor debug print

Merge pull request #1433 from sivadur/integration ...

xilinx: fix zynqmp build when tsp is enabled

xlat_v2: Fix descriptor debug print ...

The XN, PXN and UXN bits are part of the upper attributes, not the
lower attributes.

Change-Id: Ia5e83f06f2a8de88b551f55f1d36d694918ccbc0
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

plat: xilinx: zynqmp: Get chipid from registers for BL32 ...

This patch reads the chipid registers directly instead of making
pm call when running at BL32. User should ensure that these registers
should always be accessed from APU in their system configuration.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

plat: xilinx: zynqmp: Build for DDR if SPD is enabled ...

This patch builds ATF to DDR if SPD is enabled as it cant fit in
On chip memory(OCM) with SPD enabled. This solves the issue
of build failure with SPD enabled for ZynqMP platform.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

Merge pull request #1403 from glneo/for-upstream-k3 ...

TI K3 platform support

Merge pull request #1421 from Yann-lms/cpp_dtc ...

Build: add cpp build processing for dtb

Merge pull request #1413 from grandpaul/paulliu-rpi3-0 ...

rpi3: BL32 optee support

ARM Platforms: Update CNTFRQ register in CNTCTLBase frame ...

Currently TF-A doesn't initialise CNTFRQ register in CNTCTLBase
frame of the system timer. ARM ARM states that "The instance of
the register in the CNTCTLBase frame must be programmed with this
value as part of system initialization."

The psci_arch_setup() updates the CNTFRQ system register but
according to the ARM ARM, this instance of the register is
independent of the memory mapped instance. This is only an issue
for Normal world software which relies on the memory mapped
instance rather than the system register one.

This patch resolves the issue for ARM platforms.

The patch also solves a related issue on Juno, wherein
CNTBaseN.CNTFRQ can be written and does not reflect the value of
the register in CNTCTLBase frame. Hence this patch additionally
updates CNTFRQ register in the Non Secure frame of the CNTBaseN.

Fixes ARM-Software/tf-issues#593

Change-Id: I09cebb6633688b34d5b1bc349fbde4751025b350
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

Merge pull request #1423 from chandnich/sgi-575/dyncfg ...

Sgi 575/dyncfg

ti: k3: Introduce basic generic board support ...

While it would be useful to have a device tree based build, the
required components are not in place yet, so support just a simple
statically defined configuration to begin with.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>

ti: k3: common: Add PSCI stubs ...

These functions are used for the PSCI implementation and are needed to
build BL31, but we cannot implement them until we add several more drivers
related to ti-sci so these are only stubs for now.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>

ti: k3: common: Enable GICv3 support ...

Do proper initialization of GIC V3. This will allow CP15 access to GIC
from "normal world" (aka HLOS) via mrc/mcr calls.

K3 SoC family uses GICv3 compliant GIC500 without compatibility for
legacy GICv2.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>

ti: k3: common: Program A53 arch timer frequency ...

Provide K3_TIMER_FREQUENCY for the platform configuration if the GTC
clock is selected statically and override option if the platform has a
different configuration.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Benjamin Fair <b-fair@ti.com>

ti: k3: common: Add console initialization base ...

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>

ti: k3: common: Enable MMU using xlat_tables_v2 library ...

This library will be used to properly set up mappings from different
bootloaders at different exception levels. It ensures that memory mapped
devices such as UARTs are still accessible and memory regions have the
correct access permissions.

Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>

ti: k3: common: Implement topology functions ...

These functions describe the layout of the cores and clusters in order to
support the PSCI framework.

Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>

ti: k3: common: Populate BL32 and BL33 entrypoint ...

Because there is no BL2, BL31 must determine the entrypoint and memory
location of BL32 and BL33 on its own.

BL32_BASE and PRELOADED_BL33_BASE will be set in the corresponding board
makefile. We also allow a DTB address to be specified for cases when BL33
is a Linux image.

NOTE: It is possible to pull in this information from device tree as
well, however libfdt does not contain the required hooks to make this
happen at this point in time.

Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>

ti: k3: common: Add platform core management helpers ...

The K3 family of SoCs has multiple interconnects. The key interconnect
for high performance processors is the MSMC3 interconnect. This is
an io-coherent interconnect which exports multiple ports for each
processor cluster.

Sometimes, port 0 of the MSMC may not have an ARM cluster OR is isolated
such that the instance of ATF does not manage it. Define macros
in platform_def.h to help handle this.

Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>

ti: k3: Setup initial files for platform ...

Create the baseline Makefile, platform definitions file and platform
specific assembly macros file. This includes first set of constants
for the platform including cache sizes and linker format and a stub for
BL31 and the basic memory layout

K3 SoC family of processors do not use require a BL1 or BL2 binary,
since such functions are provided by an system controller on the SoC.
This lowers the burden of ATF to purely managing the local ARM cores
themselves.

Signed-off-by: Benjamin Fair <b-fair@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>

Merge pull request #1410 from Anson-Huang/master ...

Add NXP's i.MX8QX and i.MX8QM SoC support

Merge pull request #1425 from jts-arm/panic ...

Panic in BL1 when TB_FW_CONFIG is invalid