Merge changes I5693ad56,I9ddc077a into integration ...

* changes:
  mediatek: mt8183: Fix AARCH64 init fail on CPU0
  mediatek: mt8183: refine GIC driver for low power scenarios

mediatek: mt8183: Fix AARCH64 init fail on CPU0 ...

CPU0 is default on, so it doesn't need to run pwr_domain_on() at
boot. CPU0 AARCH64 will be set in pwr_domain_suspend(), but it may
encounter race condition with other CPUs.

Now AARCH64 will be set with cluster on in pwr_domain_on(), and
all CPUs on this cluster will be set together. It doesn't need to
set AARCH64 again in pwr_domain_suspend(), so the race condition
can be avoided.

Change-Id: I5693ad56e4901f82badb0fc0d8d13e4c9acfe648
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>

mediatek: mt8183: refine GIC driver for low power scenarios ...

Implement rdist save/resore functions to support low power scenarios.

Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I9ddc077a04f843275fbe2e868cdd0bd00d622de7

Merge "mediatek: mt8183: switch PLL/CLKSQ/ck_off/axi_26m control to SPM" into integration

Merge "Fix multithreaded FVP power domain tree" into integration

Merge "Add multithreaded DynamIQ dts file" into integration

Merge "GIC-600: Fix include ordering according to the coding style" into integration

GIC-600: Fix include ordering according to the coding style ...

Change-Id: Ia120bcaacea3a462ab78db13f84ed23493033601
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>

Merge changes from topic "tegra-downstream-092319" into integration ...

* changes:
  Tegra194: remove L2 ECC parity protection setting
  Tegra194: sip_calls: mark unused parameter as const
  Tegra194: implement handler to retrieve power domain tree
  Tegra194: mce: fix function declaration conflicts
  Tegra194: add macros to read GPU reset status
  Tegra194: skip notifying MCE in fake system suspend
  Tegra194: Enable system suspend

Merge changes from topic "lm/improve_memory_layout" into integration ...

* changes:
  DOC: Update ROMLIB page with memory impact info
  ROMLIB: Optimize memory layout when ROMLIB is used

DOC: Update ROMLIB page with memory impact info ...

Complete the Library at ROM documentation with information regarding
the memory impact of the feature.

Change-Id: I5a10620a8e94f123021bb19523a36d558b330deb
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

ROMLIB: Optimize memory layout when ROMLIB is used ...

ROMLIB extract functions code from BL images to put them inside ROM.
This has for effect to reduce the size of the BL images.

This patch take this size reduction into consideration to optimize the
memory layout of BL2.
A new "PLAT_ARM_BL2_ROMLIB_OPTIMIZATION" macro is defined and used to
reduce "PLAT_ARM_MAX_BL2_SIZE". This allows to remove the gap between
BL1 and BL2 when ROMLIB is used and provides more room for BL31.

The current memory gain is 0x6000 for fvp and 0x8000 for juno.

Change-Id: I71c2c2c63b57bce5b22a125efaefc486ff3e87be
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

Merge "Refactor load_auth_image_internal()." into integration

Merge "doc: Add missing terms to the glossary" into integration

Fix multithreaded FVP power domain tree ...

The number of levels in the topology has not changed but the count of
processing elements on the lowest layer is now multiplied by the value
of FVP_MAX_PE_PER_CPU.

Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: Ia1568a40ea33dbbbcdfab6c8ab6d19f4db0b8eb4

Merge "GIC-600: Fix power up sequence" into integration

GIC-600: Fix power up sequence ...

Arm's GIC-600 features a Power Register (GICR_PWRR),
which needs to be programmed to enable redistributor
operation. Section 3.6.1 in the GIC-600 TRM describes
the power-up and power-down sequence in pseudo code,
which deviates from the current TF-A implementation
in drivers/arm/gic/v3/gic600.c.
For powering on a redistributor, the pseudo code suggests
to loop over the whole sequence (check for transition,
write request bit) instead of just looping over the
ready bit read as TF-A does in gic600_pwr_on().
This patch fixes GIC-600 power up sequence according
to the TRM.

Change-Id: I445c480e96ba356b69a2d8e5308ffe6c0a97f45b
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

Merge "Coding guideline suggest not to use unsigned long" into integration

doc: Add missing terms to the glossary ...

Change-Id: Ibca94eae1a9a89c98b4d7cb5b4fd8943bf854030
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

Merge "TF-A: Fix non-standard frequency issue in udelay" into integration

TF-A: Fix non-standard frequency issue in udelay ...

Previous implementation of timers assumed that clk_div has pretty
representation in MHz (10MHz, 100MHz, etc). Unusual frequencies
(99.99MHz) were causing assertion error and made udelay unusable.

Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: Ic915fff224369d113fd9f8edbcfff169fca8beac

Refactor load_auth_image_internal(). ...

The pre-processor directives make it hard to read the non-TBB version of
this function. Refactor the code to improve readability. No functional
change introduced.

In particular, introduce a new helper function load_image_flush(),
that simply loads an image and flushes it out to main memory. This is
the only thing load_auth_image_internal() needs to do when TBB is
disabled or when authentication is dynamically disabled.

In other cases, we need to recursively authenticate the parent images up
to the root of trust. To make this clearer, this code gets moved to a
TBB-specific helper function called load_auth_image_recursive().

As a result, load_auth_image_internal() now boils down to calling the
right helper function (depending on TBB enablement and dynamic
authentication status).

Change-Id: I20a39a3b833810b97ecf4219358e7d2cac263890
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Tegra194: remove L2 ECC parity protection setting ...

This patch removes the code to enable L2 ECC parity protection
bit, as Tegra194 does not have any Cortex-A57 CPUs.

Change-Id: I4b56595fea2652e8bb8ab4a7ae7567278ecff9af
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>

Tegra194: sip_calls: mark unused parameter as const ...

This patch marks the unused parameter 'cookie', to the
plat_sip_handler() function, as const to fix an issue
flagged by the MISRA scan.

Change-Id: I53fdd2caadf43fef17fbc3a50a18bf7fdbd42d39
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra194: implement handler to retrieve power domain tree ...

This patch implements the platform handler to return the pointer
to the power domain tree.

Change-Id: I74ea7002c7a461a028b4a252bbd354256fdc0647
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra194: mce: fix function declaration conflicts ...

To fix MISRA defects, remove union in t186 MCE drivers
this driver should compatible with that.

Change-Id: I09e96a1874dd86626c7e41c92a1484a84e387402
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>

Tegra194: add macros to read GPU reset status ...

This patch adds macros to check the GPU reset status bit, before
resizing the VideoMem region.

Change-Id: I4377c1ce1ac6d3bd14c7db83526b99d72bdb41ed
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra194: skip notifying MCE in fake system suspend ...

- In pre-silicon platforms, MCE might not be ready
  to support system suspend(SC7)
- Thus, in fake system suspend mode, bypass waiting for
  MCE's acknowledgment to enter system suspend

Change-Id: Ia3c010ce080c4283ab1233ba82e3e577adca34f6
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>

Tegra194: Enable system suspend ...

This patch does the following:
1. Populate the cstate info corresponding to system suspend
   and communicate it to the MCE
2. Ask for MCE's acknowledgement for entering system suspend
   and instruct MCE to get inside system suspend once
   permitted

Change-Id: I51e1910e24a7e61e36ac2d12ce271290e433e506
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com>

Merge "docs: Add Cortex-Hercules/HerculesAE CPU support" into integration