LuminaSensum/arm-trusted-firmware

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LuminaSensum / arm-trusted-firmware

2020-10-26	d57318b Browse files » intel: common: Fix non-MISRA compliant code v2 ... This patch is used to fix remaining non compliant code for Intel SoCFPGA's mailbox and sip driver. These changes include: - Change non-interface required uint32_t into unsigned int - Change non-negative variable to unsigned int - Remove obsolete variable initialization to 0 Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I3a16c7621a5fc75eb614d97d72e44c86e7d53bf5 Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
	9e28590 Browse files » intel: mailbox: Fix non-MISRA compliant code ... This patch is used to fix remaining non compliant code for Intel SocFPGA's mailbox driver. These changes include: - adding integer literal for unsigned constant - fix non-boolean controlling expression - add braces even on conditional single statement bodies Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I0f8fd96a3540f35ee102fd2f2369b76fa73e39e1 Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
	9975604 Browse files » intel: mailbox: Mailbox error recovery handling ... Attempt to restart the mailbox if the mailbox driver not able to write any data into the mailbox command buffer. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Change-Id: Ia45291c985844dec9da82839cac701347534d32b Chee Hong Ang authored on 10 May 2020 Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
	d14e965 Browse files » intel: mailbox: Enable sending large mailbox command ... Allow mailbox command that is larger than mailbox command FIFO buffer size to be sent to SDM in multiple chunks. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I683d5f1d04c4fdf57d11ecae6232b7ed3fc49e26 Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
	4978bc2 Browse files » intel: mailbox: Use retry count in mailbox poll ... Change the main loop inside mailbox poll function from while(1) to a retry counter named sdm_loop. This is to limit the maximum possible looping of the function and prevent unexpected behaviour. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I63afad958fe5f656f6333b60d5a8b4c0ada3b23d Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
	d96e7cd Browse files » intel: mailbox: Ensure time out duration is predictive ... For each count down of time out counter, wait for number of miliseconds to ensure the time out duration is predictive. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Change-Id: I0e92dd1ef1da0ef504ec86472cf0d3c88528930b Chee Hong Ang authored on 10 May 2020 Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
	6d9f9f5 Browse files » intel: mailbox: Read mailbox response even there is an error ... Mailbox driver should read the response data if the response length in the response header is non-zero even the response header indicates error (non-zero). Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Change-Id: I928f705f43c0f46ac74b84428b830276cc4c9640 Chee Hong Ang authored on 10 May 2020 Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
	39aebd3 Browse files » intel: mailbox: Driver now handles larger response ... This patch factorizes mailbox read response from SDM into a function. Also fix the logic to support reading larger than 16 words response from SDM. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ie035ecffbbc42e12dd68061c403904c28c3b70e5 Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
	aad868b Browse files » intel: common: Change how mailbox handles job id & buffer ... This patch modifies several basic mailbox driver features to prepare for FCS enablement: - Job id management for asynchronous response - SDM command buffer full Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I78168dfb6c521d70d9cba187356b7a3c8e9b62d2 Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
2020-10-23	941fc5c Browse files » intel: common: Improve readability of mailbox read response ... Rename variables to improve readability of mailbox read response and mailbox poll response flow. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Icd33ff1d2abb28eeead15e4eb9c7f9629f8cb402 Abdul Halim, Muhammad Hadi Asyrafi committed on 23 Oct 2020
	1ae7b6f Browse files » intel: SIP: increase FPGA_CONFIG_SIZE to 32 MB ... Increase INTEL_SIP_SMC_FPGA_CONFIG_SIZE from 16 to 32MB. We need higher pre-reserved memory size between Intel service layer and secure monitor software so we can handle JIC file authorization. Signed-off-by: Richard Gong <richard.gong@intel.com> Change-Id: Ibab4e42e4b7b93a4cf741e60ec9439359ba0a64c Richard Gong authored on 13 Apr 2020 Abdul Halim, Muhammad Hadi Asyrafi committed on 23 Oct 2020
	d191eb2 Browse files » intel: common: Remove urgent from mailbox async ... Remove urgent argument from asynchrounous mailbox command as any urgent command should always be synchronous Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Iaa64335db24df3a562470d0d1c3d6a3a71493319 Abdul Halim, Muhammad Hadi Asyrafi committed on 23 Oct 2020
	f8e6a09 Browse files » intel: common: Improve mailbox driver readability ... Use pre-defined macros for return values and common mailbox arguments Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I5d549ee5358aebadf909f79fda55e83ee9844a0e Abdul Halim, Muhammad Hadi Asyrafi committed on 23 Oct 2020
	516f322 Browse files » intel: common: Clean up mailbox and sip header ... Sort and rearrange definitions in both mailbox and sip header to increase readability and maintainability. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I5544c2f17efdf3174757c55afd8cc1062fbae856 Abdul Halim, Muhammad Hadi Asyrafi committed on 23 Oct 2020
	7f56f24 Browse files » intel: clear 'PLAT_SEC_ENTRY' in early platform setup ... Ensure 'PLAT_SEC_ENTRY' is cleared during early platform setup. This is to prevent the slave CPU cores jump to the stale entry point after warm reset when using U-Boot SPL as first stage boot loader. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Change-Id: I3294ce2f74aa691d0cf311fa30f27f9d4fb8800a Chee Hong Ang authored on 24 Apr 2020 Abdul Halim, Muhammad Hadi Asyrafi committed on 23 Oct 2020
	95fca11 Browse files » Merge "docs: marvell: update ddr3 build instructions" into integration Varun Wadekar authored on 23 Oct 2020 TrustedFirmware Code Review committed on 23 Oct 2020
	9c28689 Browse files » Merge changes I5ae9d08b,I5cbbd7eb,Idb389223 into integration ... * changes: plat: marvell: armada: Building ${DOIMAGETOOL} is only for a8k plat: marvell: armada: Fix including plat/marvell/marvell.mk file plat: marvell: armada: a3k: When WTP is empty do not define variables and targets which depends on it Varun Wadekar authored on 23 Oct 2020 TrustedFirmware Code Review committed on 23 Oct 2020
2020-10-22	083dbb6 Browse files » Merge "plat/qemu_sbsa: Remove cortex_a53 and aem_generic" into integration Manish Pandey authored on 22 Oct 2020 TrustedFirmware Code Review committed on 22 Oct 2020
2020-10-21	bc98a2e Browse files » Merge changes from topic "tc0_sel2_spmc" into integration ... * changes: plat: tc0: Configure TZC with secure world regions plat: tc0: Enable SPMC execution at S-EL2 plat: tc0: Add TZC DRAM1 region for SPMC and trusted OS plat: arm: Make BL32_BASE platform dependent when SPD_spmd is enabled plat: tc0: Disable SPE Manish Pandey authored on 21 Oct 2020 TrustedFirmware Code Review committed on 21 Oct 2020
	c4d919e Browse files » Merge changes from topic "tc0_sel2_spmc" into integration ... * changes: lib: el3_runtime: Fix SPE system registers in el2_sysregs_context lib: el3_runtime: Conditionally save/restore EL2 NEVE registers lib: el3_runtime: Fix aarch32 system registers in el2_sysregs_context Manish Pandey authored on 21 Oct 2020 TrustedFirmware Code Review committed on 21 Oct 2020
	d1ff30d Browse files » plat/qemu_sbsa: Remove cortex_a53 and aem_generic ... The qemu_sbsa platform uses 42bit address size but the cortex-a53 only supports 40bit addressing, the cpu is incompatible with the platform. The aem_generic is also not used with qemu_sbsa, in fact, the platform currently only properly supports the cortex-a57 cpu. Change-Id: I91c92533116f1c3451d01ca99824e91d3d58df14 Signed-off-by: Tomas Pilar <tomas@nuviateam.com> Tomas Pilar committed on 21 Oct 2020
	b5e3d54 Browse files » plat: marvell: armada: Building ${DOIMAGETOOL} is only for a8k ... Currently a3k target is misusing ${DOIMAGETOOL} target for building flash and UART images. It is not used for building image tool. So move ${DOIMAGETOOL} target from common marvell include file into a8k include file and add correct invocation of ${MAKE} into a3k for building flash and UART images. Part of this change is also checks that MV_DDR_PATH for a3k was specified by user as this option is required for building a3k flash and UART images. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I5ae9d08b8505460933f17836c9b6435fd6e51bb6 Pali Rohár committed on 21 Oct 2020
2020-10-20	bd260fc Browse files » Merge "docs: code review guidelines" into integration Manish Pandey authored on 20 Oct 2020 TrustedFirmware Code Review committed on 20 Oct 2020
	879b5b8 Browse files » plat: tc0: Configure TZC with secure world regions ... This includes configuration for SPMC and trusted OS. Change-Id: Ie24df200f446b3f5b23f5f764b115c7191e6ada3 Signed-off-by: Usama Arif <usama.arif@arm.com> Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Usama Arif authored on 26 Aug 2020 Manish Pandey committed on 20 Oct 2020
	b0d1275 Browse files » plat: tc0: Enable SPMC execution at S-EL2 ... This patch enables SPMC execution at S-EL2 by adding below changes - Map TC0_MAP_TZC_DRAM1 for loading SPMC - Add details of cactus test secure partitions - Adds tc0 spmc manifest file with details on secure partitions - Inlcude TOS_FW_CONFIG when SPM is spmd - Increases bl2 image size SPMC at S-EL2 is only enabled when build with SPD=spmd. Change-Id: I4c5f70911903c232ee8ecca57f1e288d6b1cd647 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Arunachalam Ganapathy authored on 22 Sep 2020 Manish Pandey committed on 20 Oct 2020
	a3ecbb3 Browse files » plat: tc0: Add TZC DRAM1 region for SPMC and trusted OS ... - Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for TC0_TZC_DRAM1 - Add TC0_NS_DRAM1 base and mapping - Reserve memory region in tc0.dts Change-Id: If2431f7f68e4255e28c86a0e89637dab7c424a13 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Arunachalam Ganapathy authored on 22 Sep 2020 Manish Pandey committed on 20 Oct 2020
	d32113c Browse files » plat: arm: Make BL32_BASE platform dependent when SPD_spmd is enabled ... To support platforms without Trusted DRAM this patch defines PLAT_ARM_SPMC_BASE and enables platform to use either Trusted DRAM or DRAM region behind TZC. Change-Id: Icaa5c7d33334258ff27e8e0bfd0812c304e68ae4 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Arunachalam Ganapathy authored on 27 Jul 2020 Manish Pandey committed on 20 Oct 2020
	c398caf Browse files » plat: tc0: Disable SPE ... Statistical Profiling Extension is not supported by Matterhorn core Change-Id: Iec652f1c6d6b6a9bf118ba682276a7c70a6abc0d Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Arunachalam Ganapathy authored on 28 May 2020 Manish Pandey committed on 20 Oct 2020
	2b036b7 Browse files » lib: el3_runtime: Fix SPE system registers in el2_sysregs_context ... Include EL2 registers related to SPE in EL2 context save/restore routines if architecture supports it and platform wants to use these features in Secure world. Change-Id: Ie01a2c38fa5f6c907276eddec120fdfb222561a6 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Arunachalam Ganapathy authored on 9 Oct 2020 Manish Pandey committed on 20 Oct 2020
	062f8aa Browse files » lib: el3_runtime: Conditionally save/restore EL2 NEVE registers ... Include EL2 registers related to Nested Virtualization in EL2 context save/restore routines if architecture supports it and platform wants to use these features in Secure world. Change-Id: If006ab83bbc2576488686f5ffdff88b91adced5c Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Arunachalam Ganapathy authored on 28 May 2020 Manish Pandey committed on 20 Oct 2020