LuminaSensum/arm-trusted-firmware

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LuminaSensum / arm-trusted-firmware

2020-01-23	a0cacc9 Browse files » Tegra194: memctrl: Disable PVARDC coalescer ... Due to a hardware bug PVA may perform memory transactions which cause coalescer faults. This change works around the issue by disabling coalescer for PVA0RDC and PVA1RDC. Change-Id: I27d1f6e7bc819fb303dae98079d9277fa346a1d3 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Arto Merilainen authored on 18 Jan 2018 Varun Wadekar committed on 23 Jan 2020
	21e22fe Browse files » Tegra194: memctrl: force seswr/rd transactions as passsthru & coherent ... Force memory transactions from seswr and sesrd as coherent_snoop from no-override. This is necessary as niso clients should use coherent path. Presently its set as FORCE_COHERENT_SNOOP. Once SE+TZ is enabled with SMMU, this needs to be replaced by FORCE_COHERENT. Change-Id: I8b50722de743b9028129b4715769ef93deab73b5 Signed-off-by: Puneet Saxena <puneets@nvidia.com> Puneet Saxena authored on 2 Jan 2018 Varun Wadekar committed on 23 Jan 2020
	1a7a1dc Browse files » Tegra194: Request CG7 from last core in cluster ... - SC7 requires all the cluster groups to be in CG7 state, else is_sc7_allowed will get denied - As a WAR while requesting CC6, request CG7 as well - CG7 request will not be honored if it is not last core in Cluster group - This is just to satisfy MCE for now as CG7 is going to be defeatured Change-Id: Ibf2f8a365a2e46bd427abd563da772b6b618350f Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com> Vignesh Radhakrishnan authored on 28 Dec 2017 Varun Wadekar committed on 23 Jan 2020
	d11f5e0 Browse files » Tegra194: toggle SE clock during context save/restore ... This patch adds support to toggle SE clock, using the bpmp_ipc interface, to enable SE context save/restore. The SE sequence mostly gets called during System Suspend/Resume. Change-Id: I9cee12a9e14861d5e3c8c4f18b4d7f898b6ebfa7 Signed-off-by: steven kao <skao@nvidia.com> steven kao authored on 2 Jan 2018 Varun Wadekar committed on 23 Jan 2020
	fdc8021 Browse files » Tegra: bpmp: fix header file paths ... This patch fixes the header file paths to include debug.h from the right location. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: If303792d2169158f436ae6aa5b6d7a4f88e28f7b Varun Wadekar committed on 23 Jan 2020
	4302e04 Browse files » Merge "Revert "Changes necessary to support SEPARATE_NOBITS_REGION feature"" into integration Mark Dykes authored on 23 Jan 2020 TrustedFirmware Code Review committed on 23 Jan 2020
	0908c31 Browse files » Merge "Revert "plat/arm: Add support for SEPARATE_NOBITS_REGION"" into integration Mark Dykes authored on 23 Jan 2020 TrustedFirmware Code Review committed on 23 Jan 2020
	3c6ec8f Browse files » Revert "plat/arm: Add support for SEPARATE_NOBITS_REGION" ... This reverts commit `d433bbd`. Change-Id: I46c69dce704a1ce1b50452dd4d62425c4a67f7f0 Mark Dykes committed on 23 Jan 2020
	5117a53 Browse files » Merge "Errata workarounds N1 1043202, 1315703 default off" into integration Alexei Fedorov authored on 23 Jan 2020 TrustedFirmware Code Review committed on 23 Jan 2020
	dbafda7 Browse files » Errata workarounds N1 1043202, 1315703 default off ... Setting errata workarounds for N1 1043202 and 1315703 to 0 since they should be turned off by default. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I116673a4ddcf64436e90d70133f035a133989ed9 laurenw-arm authored on 22 Jan 2020 Olivier Deprez committed on 23 Jan 2020
	a74185b Browse files » Merge "spm-mm: correcting instructions to build SPM for FVP" into integration Manish Pandey authored on 23 Jan 2020 TrustedFirmware Code Review committed on 23 Jan 2020
	09035d1 Browse files » spm-mm: correcting instructions to build SPM for FVP ... Out of two possible implementation of Secure Partition Manager(SPM) currently only Management mode (MM) design is supported and the support for SPM based on SPCI Alpha 1 prototype has been removed. Earlier both implementation used common build flag "ENABLE_SPM" but it has since been decoupled and MM uses a separate build FLAG "SPM_MM". Instructions to build it for FVP was still using "ENABLE_SPM", which has beend corrected in this patch. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I505b98173d6051816436aa602ced6dbec4efc776 Manish Pandey committed on 23 Jan 2020
	31ce893 Browse files » xilinx: versal: PLM to ATF handover ... Parse the parameter structure the PLM populates, to populate the bl32 and bl33 image structures. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Change-Id: I317072d1086f6cc6f90883c1b8b6d086ff57b443 Venkatesh Yadav Abbarapu committed on 23 Jan 2020
	4d9f825 Browse files » xilinx: common: Move ATF handover to common file ... ATF handover can be used by Xilinx platforms, so move it to common file from platform specific files. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Change-Id: I5f0839351f534619de581d1953c8427a079487e0 Venkatesh Yadav Abbarapu committed on 23 Jan 2020
2020-01-22	3b5454e Browse files » Revert "Changes necessary to support SEPARATE_NOBITS_REGION feature" ... This reverts commit `76d84cb`. Change-Id: I867af7af3d9f5e568101f79b9ebea578e5cb2a4b Mark Dykes committed on 22 Jan 2020
	29d1374 Browse files » Merge "plat/arm: Add support for SEPARATE_NOBITS_REGION" into integration Mark Dykes authored on 22 Jan 2020 TrustedFirmware Code Review committed on 22 Jan 2020
	aa386f7 Browse files » Merge "Changes necessary to support SEPARATE_NOBITS_REGION feature" into integration Mark Dykes authored on 22 Jan 2020 TrustedFirmware Code Review committed on 22 Jan 2020
	f461fe3 Browse files » Prevent speculative execution past ERET ... Even though ERET always causes a jump to another address, aarch64 CPUs speculatively execute following instructions as if the ERET instruction was not a jump instruction. The speculative execution does not cross privilege-levels (to the jump target as one would expect), but it continues on the kernel privilege level as if the ERET instruction did not change the control flow - thus execution anything that is accidentally linked after the ERET instruction. Later, the results of this speculative execution are always architecturally discarded, however they can leak data using microarchitectural side channels. This speculative execution is very reliable (seems to be unconditional) and it manages to complete even relatively performance-heavy operations (e.g. multiple dependent fetches from uncached memory). This was fixed in Linux, FreeBSD, OpenBSD and Optee OS: https://github.com/torvalds/linux/commit/679db70801da9fda91d26caf13bf5b5ccc74e8e8 https://github.com/freebsd/freebsd/commit/29fb48ace4186a41c409fde52bcf4216e9e50b61 https://github.com/openbsd/src/commit/3a08873ece1cb28ace89fd65e8f3c1375cc98de2 https://github.com/OP-TEE/optee_os/commit/abfd092aa19f9c0251e3d5551e2d68a9ebcfec8a It is demonstrated in a SafeSide example: https://github.com/google/safeside/blob/master/demos/eret_hvc_smc_wrapper.cc https://github.com/google/safeside/blob/master/kernel_modules/kmod_eret_hvc_smc/eret_hvc_smc_module.c Signed-off-by: Anthony Steinhauser <asteinhauser@google.com> Change-Id: Iead39b0b9fb4b8d8b5609daaa8be81497ba63a0f Anthony Steinhauser committed on 22 Jan 2020
	d81e38f Browse files » Merge "FDT helper functions: Fix MISRA issues" into integration Sandrine Bailleux authored on 22 Jan 2020 TrustedFirmware Code Review committed on 22 Jan 2020
	f44d291 Browse files » Merge changes from topic "add-versal-soc-support" into integration ... * changes: plat: xilinx: Move pm_client.h to common directory plat: xilinx: versal: Make silicon default build target xilinx: versal: Wire silicon default setup versal: Increase OCM memory size for DEBUG builds plat: xilinx: versal: Dont set IOU switch clock arm64: versal: Adjust cpu clock for versal virtual xilinx: versal: Add support for PM_GET_OPERATING_CHARACTERISTIC EEMI call plat: versal: Add Get_ChipID API plat: xilinx: versal: Add load Pdi API support xilinx: versal: Add feature check API xilinx: versal: Implement set wakeup source for client plat: xilinx: versal: Add GET_CALLBACK_DATA function xilinx: versal: Add PSCI APIs for system shutdown & reset xilinx: versal: Add PSCI APIs for suspend/resume xilinx: versal: Remove no_pmc ops to ON power domain xilinx: versal: Add set wakeup source API xilinx: versal: Add client wakeup API xilinx: versal: Add query data API xilinx: versal: Add request wakeup API xilinx: versal: Add PM_INIT_FINALIZE API for versal xilinx: versal: Add support of PM_GET_TRUSTZONE_VERSION API xilinx: versal: enable ipi mailbox service xilinx: move ipi mailbox svc to xilinx common plat: xilinx: versal: Implement PM IOCTL API xilinx: versal: Implement power down/restart related EEMI API xilinx: versal: Add SMC handler for EEMI API xilinx: versal: Implement PLL related PM APIs xilinx: versal: Implement clock related PM APIs xilinx: versal: Implement pin control related PM APIs xilinx: versal: Implement reset related PM APIs xilinx: versal: Implement device related PM APIs xilinx: versal: Add support for suspend related APIs xilinx: versal: Add get_api_version support xilinx: Add support to send PM API to PMC using IPI for versal plat: xilinx: versal: Move versal_def.h to include directory plat: xilinx: versal: Move versal_private.h to include directory plat: xilinx: zynqmp: Use GIC framework for warm restart Soby Mathew authored on 22 Jan 2020 TrustedFirmware Code Review committed on 22 Jan 2020
	67878cb Browse files » Xilinx zynqmp: add missing pin control group for ethernet 0. ... Signed-off-by: Norbert Werner <opensource@lab-w.org> Change-Id: I3264515e5901689328861964ff664ff08b6e852c Norbert Werner authored on 19 Jan 2020 Olivier Deprez committed on 22 Jan 2020
	c3fc368 Browse files » xlat_tables_v2: simplify end address checks in mmap_add_region_check() ... Use end_va and end_pa defined at the beginning of this function. Change-Id: I0e8b3b35fceb87b5d35397eb892d4fe92ba90b4c Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Masahiro Yamada committed on 22 Jan 2020
	c9c0b66 Browse files » Merge "Set lld as the default linker for Clang builds" into integration Sandrine Bailleux authored on 22 Jan 2020 TrustedFirmware Code Review committed on 22 Jan 2020
	feb358b Browse files » FDT helper functions: Fix MISRA issues ... Moving the FDT helper functions to the common/ directory exposed the file to MISRA checking, which is mandatory for common code. Fix the complaints that the test suite reported. Change-Id: Ica8c8a95218bba5a3fd92a55407de24df58e8476 Signed-off-by: Andre Przywara <andre.przywara@arm.com> Andre Przywara authored on 16 Sep 2019 Sandrine Bailleux committed on 22 Jan 2020
2020-01-21	d433bbd Browse files » plat/arm: Add support for SEPARATE_NOBITS_REGION ... In order to support SEPARATE_NOBITS_REGION for Arm platforms, we need to load BL31 PROGBITS into secure DRAM space and BL31 NOBITS into SRAM. Hence mandate the build to require that ARM_BL31_IN_DRAM is enabled as well. Naturally with SEPARATE_NOBITS_REGION enabled, the BL31 initialization code cannot be reclaimed to be used for runtime data such as secondary cpu stacks. Memory map for BL31 NOBITS region also has to be created. Change-Id: Ibd480f82c1dc74e9cbb54eec07d7a8fecbf25433 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Madhukar Pappireddy committed on 21 Jan 2020
	76d84cb Browse files » Changes necessary to support SEPARATE_NOBITS_REGION feature ... Since BL31 PROGBITS and BL31 NOBITS sections are going to be in non-adjacent memory regions, potentially far from each other, some fixes are needed to support it completely. 1. adr instruction only allows computing the effective address of a location only within 1MB range of the PC. However, adrp instruction together with an add permits position independent address of any location with 4GB range of PC. 2. Since BL31 _RW_END_ marks the end of BL31 image, care must be taken that it is aligned to page size since we map this memory region in BL31 using xlat_v2 lib utils which mandate alignment of image size to page granularity. Change-Id: Ic745c5a130fe4239fa2742142d083b2bdc4e8b85 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Madhukar Pappireddy committed on 21 Jan 2020
	e5eaf88 Browse files » Merge "Replace dts includes with C preprocessor syntax" into integration Manish Pandey authored on 21 Jan 2020 TrustedFirmware Code Review committed on 21 Jan 2020
	22eaa87 Browse files » Merge "cert_create: Remove some unused header files inclusions" into integration Olivier Deprez authored on 21 Jan 2020 TrustedFirmware Code Review committed on 21 Jan 2020
	b449642 Browse files » Merge "allwinner: Clean up MMU setup" into integration Manish Pandey authored on 21 Jan 2020 TrustedFirmware Code Review committed on 21 Jan 2020
	004c922 Browse files » Merge changes Ib1ed9786,I6c4855c8 into integration ... * changes: plat: imx: Correct the SGIs that used for secure interrupt plat: imx8mm: Add the support for opteed spd on imx8mq/imx8mm Sandrine Bailleux authored on 21 Jan 2020 TrustedFirmware Code Review committed on 21 Jan 2020