intel: Extend SiP service to support mailbox's RSU ...

Introduce support for RSU that can be initiated through SMC calls.

Added features as below:
- RSU status
- RSU update
- RSU HPS notify
- RSU get sub-partition

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I78d5a07688e43da99f03d77dfd45ffb4a78f2e4c

Merge "Coverity: remove unnecessary header file includes" into integration

Merge changes from topic "mp/separate_nobits" into integration ...

* changes:
  plat/arm: Add support for SEPARATE_NOBITS_REGION
  Changes necessary to support SEPARATE_NOBITS_REGION feature

Coverity: remove unnecessary header file includes ...

This patch removes unnecessary header file includes
discovered by Coverity HFA option.

Change-Id: I2827c37c1c24866c87db0e206e681900545925d4
Signed-off-by: Zelalem <zelalem.aweke@arm.com>

Merge "intel: agilex: Enable uboot BL31 loading" into integration

Merge "FDT wrappers: add functions for read/write bytes" into integration

FDT wrappers: add functions for read/write bytes ...

This patch adds 'fdtw_read_bytes' and 'fdtw_write_inplace_bytes'
functions for read/write array of bytes from/to a given property.
It also adds 'fdt_setprop_inplace_namelen_partial' to jmptbl.i
files for builds with USE_ROMLIB=1 option.

Change-Id: Ied7b5c8b38a0e21d508aa7bcf5893e656028b14d
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

Merge "Use correct type when reading SCR register" into integration

Merge changes from topic "sb/select-cot" into integration ...

* changes:
  Introduce COT build option
  cert_create: Remove references to TBBR in common code
  cert_create: Introduce COT build option
  cert_create: Introduce TBBR CoT makefile

Introduce COT build option ...

Allows to select the chain of trust to use when the Trusted Boot feature
is enabled. This affects both the cert_create tool and the firmware
itself.

Right now, the only available CoT is TBBR.

Change-Id: I7ab54e66508a1416cb3fcd3dfb0f055696763b3d
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

qemu: Implement PSCI_CPU_OFF. ...

This is based on the rpi implementation from
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/2746.

Signed-off-by: Andrew Walbran <qwandor@google.com>
Change-Id: I5fe324fcd9d5e232091e01267ea12147c46bc9c1

Merge changes I0fb7cf79,Ia8eb4710 into integration ...

* changes:
  qemu: Implement qemu_system_off via semihosting.
  qemu: Support ARM_LINUX_KERNEL_AS_BL33 to pass FDT address.

intel: agilex: Enable uboot BL31 loading ...

This patch enables uboot's spl entrypoint to BL31 and also handles
secondary cpus state during cold boot.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib70ec91a3ad09a568cb66e7c1e23a2b3e460746c

Enable -Wredundant-decls warning check ...

This flag warns if anything is declared more than once in the same
scope, even in cases where multiple declaration is valid and changes
nothing.

Consequently, this patch also fixes the issues reported by this
flag. Consider the following two lines of code from two different source
files(bl_common.h and bl31_plat_setup.c):

IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE);
IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE);

The IMPORT_SYM macro which actually imports a linker symbol as a C expression.
The macro defines the __RO_START__ as an extern variable twice, one for each
instance. __RO_START__ symbol is defined by the linker script to mark the start
of the Read-Only area of the memory map.

Essentially, the platform code redefines the linker symbol with a different
(relevant) name rather than using the standard symbol. A simple solution to
fix this issue in the platform code for redundant declarations warning is
to remove the second IMPORT_SYM and replace it with following assignment

static const unsigned long BL2_RO_BASE = BL_CODE_BASE;

Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

Use correct type when reading SCR register ...

The Secure Configuration Register is 64-bits in AArch64 and 32-bits in
AArch32. Use u_register_t instead of unsigned int to reflect this.

Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

Merge changes from topic "ti-cluster-power" into integration ...

* changes:
  ti: k3: drivers: ti_sci: Put sequence number in coherent memory
  ti: k3: drivers: ti_sci: Remove indirect structure of const data
  ti: k3: common: Enable ARM cluster power down
  ti: k3: common: Rename device IDs to be more consistent

Merge "plat/arm/sgi: move topology information to board folder" into integration

Tegra194: enable spe-console functionality ...

This patch enables the config to switch to the console provided
by the SPE firmware.

Change-Id: I5a3bed09ee1e84f958d0925501d1a79fb7f694de
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

plat/arm: Add support for SEPARATE_NOBITS_REGION ...

In order to support SEPARATE_NOBITS_REGION for Arm platforms, we need to load
BL31 PROGBITS into secure DRAM space and BL31 NOBITS into SRAM. Hence mandate
the build to require that ARM_BL31_IN_DRAM is enabled as well.

Naturally with SEPARATE_NOBITS_REGION enabled, the BL31 initialization code
cannot be reclaimed to be used for runtime data such as secondary cpu stacks.

Memory map for BL31 NOBITS region also has to be created.

Change-Id: Ibbc8c9499a32e63fd0957a6e254608fbf6fa90c9
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

ti: k3: drivers: ti_sci: Put sequence number in coherent memory ...

The current message sequence number is accessed both with caches on and
off so put this memory in the un-cached coherent section so accesses
are consistent and coherency is maintained.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Ieeefefeaffc691e4e4c4de7c74490d50ff9de807

ti: k3: drivers: ti_sci: Remove indirect structure of const data ...

The 'info' structure contained what is only static data for this
implementation of TI-SCI. Remove this indirection and remove the
struct.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I2328fddf388bf7d56a56bd673c080e78c86fe072

ti: k3: common: Enable ARM cluster power down ...

When all cores in a cluster are powered down the parent cluster can
be also powered down. When the last core has requested powering down
follow by sending the cluster power down sequence to the system
power controller firmware.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I0ffeb339852c66ef62743aecd3e17ca20bad6216

ti: k3: common: Rename device IDs to be more consistent ...

The core number is called 'core_id' but the processor and device IDs are
called 'proc' and 'device'. Rename these to make them less confusing.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I3d7c6dddd7aa37b5dee1aa9689ce31730e9c3b59

Merge changes from topic "pie" into integration ...

* changes:
  uniphier: make all BL images completely position-independent
  uniphier: make uniphier_mmap_setup() work with PIE
  uniphier: pass SCP base address as a function parameter
  uniphier: set buffer offset and length for io_block dynamically
  uniphier: use more mmap_add_dynamic_region() for loading images
  bl_common: add BL_END macro
  uniphier: turn on ENABLE_PIE
  TSP: add PIE support
  BL2_AT_EL3: add PIE support
  BL31: discard .dynsym .dynstr .hash sections to make ENABLE_PIE work
  PIE: pass PIE options only to BL31
  Build: support per-BL LDFLAGS

plat/arm/sgi: move topology information to board folder ...

The platform topology description of the upcoming Arm's RD platforms
have different topology than those listed in the sgi_topology.c file. So
instead of adding platform specific topology into existing
sgi_topology.c file, those can be added to respective board files. In
order to maintain consistency with the upcoming platforms, move the
existing platform topology description to respective board files.

Change-Id: I4689c7d24cd0c75a3dc234370c34a85c08598abb
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>

Merge "plat/sgm: Always use SCMI for SGM platforms" into integration

Merge "xilinx: Unify Platform specific defines for PSCI module" into integration

plat/sgm: Always use SCMI for SGM platforms ...

As on SGI platforms, SCPI is unsupported on SGM platforms.

Change-Id: I556ed095b9eb55b72447230ee2725d3c76160a08
Signed-off-by: Chris Kay <chris.kay@arm.com>

xilinx: Unify Platform specific defines for PSCI module ...

PLATFORM_CORE_COUNT - Unsigned int
PLATFORM_CLUSTER_COUNT - Unsigned int
PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int
PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int

Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I76f5535f1cbdaf3fc1235cd824111d9afe8f7e1b

uniphier: make all BL images completely position-independent ...

This platform supports multiple SoCs. The next SoC will still keep
quite similar architecture, but the memory base will be changed.

The ENABLE_PIE improves the maintainability and usability. You can reuse
a single set of BL images for other SoC/board without re-compiling TF-A
at all. This will also keep the code cleaner because it avoids #ifdef
around various base addresses.

By defining ENABLE_PIE, BL2_AT_EL3, BL31, and BL32 (TSP) are really
position-independent now. You can load them anywhere irrespective of
their link address.

Change-Id: I8d5e3124ee30012f5b3bfa278b0baff8efd2fff7
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>