2015-06-24 |
Merge pull request #310 from sandrine-bailleux/sb/tf-issue-304-phase1
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Enhance BL3-1 entrypoint handling to support non-TF boot firmware - Phase 1
danh-arm
committed
on 24 Jun 2015
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2015-06-12 |
Merge pull request #317 from vwadekar/run-bl32-on-tegra-v3
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Run bl32 on tegra v3
Achin Gupta
committed
on 12 Jun 2015
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2015-06-11 |
Move dispatcher documents to the docs/spd folder
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This patch moves the optee-dispatcher.md and tlk-dispatcher.md to
docs/spd.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 11 Jun 2015
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Boot Trusted OS' on Tegra SoCs
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This patch adds support to run a Trusted OS during boot time. The
previous stage bootloader passes the entry point information in
the 'bl32_ep_info' structure, which is passed over to the SPD.
The build system expects the dispatcher to be passed as an input
parameter using the 'SPD=<dispatcher>' option. The Tegra docs have
also been updated with this information.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 11 Jun 2015
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2015-06-08 |
Fix build option 'ARM_TSP_RAM_LOCATION' in user guide
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The 'ARM_TSP_RAM_LOCATION_ID' option specified in the user guide
corresponds to the internal definition not visible to the final
user. The proper build option is 'ARM_TSP_RAM_LOCATION'. This
patch fixes it.
Fixes ARM-software/tf-issues#308
Change-Id: Ica8cb72c0c5e8b3503f60b5357d16698e869b1bd
Juan Castillo
committed
on 8 Jun 2015
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2015-06-04 |
Introduce PROGRAMMABLE_RESET_ADDRESS build option
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This patch introduces a new platform build option, called
PROGRAMMABLE_RESET_ADDRESS, which tells whether the platform has
a programmable or fixed reset vector address.
If the reset vector address is fixed then the code relies on the
platform_get_entrypoint() mailbox mechanism to figure out where
it is supposed to jump. On the other hand, if it is programmable
then it is assumed that the platform code will program directly
the right address into the RVBAR register (instead of using the
mailbox redirection) so the mailbox is ignored in this case.
Change-Id: If59c3b11fb1f692976e1d8b96c7e2da0ebfba308
Sandrine Bailleux
committed
on 4 Jun 2015
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Rationalize reset handling code
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The attempt to run the CPU reset code as soon as possible after reset
results in highly complex conditional code relating to the
RESET_TO_BL31 option.
This patch relaxes this requirement a little. In the BL1, BL3-1 and
PSCI entrypoints code, the sequence of operations is now as follows:
1) Detect whether it is a cold or warm boot;
2) For cold boot, detect whether it is the primary or a secondary
CPU. This is needed to handle multiple CPUs entering cold reset
simultaneously;
3) Run the CPU init code.
This patch also abstracts the EL3 registers initialisation done by
the BL1, BL3-1 and PSCI entrypoints into common code.
This improves code re-use and consolidates the code flows for
different types of systems.
NOTE: THE FUNCTION plat_secondary_cold_boot() IS NOW EXPECTED TO
NEVER RETURN. THIS PATCH FORCES PLATFORM PORTS THAT RELIED ON THE
FORMER RETRY LOOP AT THE CALL SITE TO MODIFY THEIR IMPLEMENTATION.
OTHERWISE, SECONDARY CPUS WILL PANIC.
Change-Id: If5ecd74d75bee700b1bd718d23d7556b8f863546
Sandrine Bailleux
committed
on 4 Jun 2015
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Remove FIRST_RESET_HANDLER_CALL build option
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This patch removes the FIRST_RESET_HANDLER_CALL build flag and its
use in ARM development platforms. If a different reset handling
behavior is required between the first and subsequent invocations
of the reset handling code, this should be detected at runtime.
On Juno, the platform reset handler is now always compiled in.
This means it is now executed twice on the cold boot path, first in
BL1 then in BL3-1, and it has the same behavior in both cases. It is
also executed twice on the warm boot path, first in BL1 then in the
PSCI entrypoint code.
Also update the documentation to reflect this change.
NOTE: THIS PATCH MAY FORCE PLATFORM PORTS THAT USE THE
FIRST_RESET_HANDLER_CALL BUILD OPTION TO FIX THEIR RESET HANDLER.
Change-Id: Ie5c17dbbd0932f5fa3b446efc6e590798a5beae2
Sandrine Bailleux
committed
on 4 Jun 2015
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2015-06-01 |
Always enable CCI coherency in BL3-1
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On ARM standard platforms, snoop and DVM requests used to be enabled
for the primary CPU's cluster only in the first EL3 bootloader.
In other words, if the platform reset into BL1 then CCI coherency
would be enabled by BL1 only, and not by BL3-1 again.
However, this doesn't cater for platforms that use BL3-1 along with
a non-TF ROM bootloader that doesn't enable snoop and DVM requests.
In this case, CCI coherency is never enabled.
This patch modifies the function bl31_early_platform_setup() on
ARM standard platforms so that it always enables snoop and DVM
requests regardless of whether earlier bootloader stages have
already done it. There is no harm in executing this code twice.
ARM Trusted Firmware Design document updated accordingly.
Change-Id: Idf1bdeb24d2e1947adfbb76a509f10beef224e1c
Sandrine Bailleux
committed
on 1 Jun 2015
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2015-05-29 |
Support for NVIDIA's Tegra T210 SoCs
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T210 is the latest chip in the Tegra family of SoCs from NVIDIA. It is an
ARM v8 dual-cluster (A57/A53) SoC, with any one of the clusters being active
at a given point in time.
This patch adds support to boot the Trusted Firmware on T210 SoCs. The patch
also adds support to boot secondary CPUs, enter/exit core power states for
all CPUs in the slow/fast clusters. The support to switch between clusters
is still not available in this patch and would be available later.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 29 May 2015
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2015-04-29 |
Move up dependency versions in user guide
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Move up the version numbers in the user guide of:
* DS-5 (to v5.21)
* EDK2 (to v3.0)
* Linux Kernel (to 1.6-Juno)
* Linaro file-system (to 15.03)
* Juno SCP binary (to v1.7.0 within board recovery image 0.11.3).
Change-Id: Ieb09e633acc2b33823ddf35f77f44e7da60b99ba
Sandrine Bailleux
committed
on 29 Apr 2015
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2015-04-28 |
Detect SCP version incompatibility
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There has been a breaking change in the communication protocols used
between the AP cores and the SCP on CSS based platforms like Juno.
This means both the AP Trusted Firmware and SCP firmware must be
updated at the same time.
In case the user forgets to update the SCP ROM firmware, this patch
detects when it still uses the previous version of the communication
protocol. It will then output a comprehensive error message that helps
trouble-shoot the issue.
Change-Id: I7baf8f05ec0b7d8df25e0ee53df61fe7be0207c2
Sandrine Bailleux
authored
on 13 Apr 2015
Dan Handley
committed
on 28 Apr 2015
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Doc updates following platform port reorganization
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Update the User Guide, Porting Guide and Firmware Design documents
to align them with the recent changes made to the FVP and Juno
platform ports.
Also fix some other historical inaccuracies.
Change-Id: I37aba4805f9044b1a047996d3e396c75f4a09176
Dan Handley
committed
on 28 Apr 2015
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2015-04-01 |
Merge pull request #280 from vwadekar/tlkd-fixed-v3
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TLK dispatcher
danh-arm
committed
on 1 Apr 2015
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2015-03-31 |
TLK-D documentation and add NVIDIA to the Acknowledgements file
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Include TLK Dispatcher's documentation and add NVIDIA to the
Acknowledgements file. TLK is now a supported Trusted OS with
the Trusted Firmware.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 31 Mar 2015
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2015-03-17 |
Merge pull request #269 from vikramkanigiri/vk/common-cci
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Common driver for ARM cache coherent Interconnects
danh-arm
committed
on 17 Mar 2015
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Merge pull request #267 from sandrine-bailleux/sb/doc-fixes
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Documentation fixes in 'make help' message and User Guide
danh-arm
committed
on 17 Mar 2015
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2015-03-16 |
Common driver for ARM Cache Coherent Interconnects
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Even though both CCI-400 and CCI-500 IPs have different configurations
with respect to the number and types of supported interfaces, their
register offsets and programming sequences are similar. This patch
creates a common driver for enabling and disabling snoop transactions
and DVMs with both the IPs.
New platform ports which implement one of these IPs should use this
common driver. Existing platform ports which implement CCI-400 should
migrate to the common driver as the standalone CCI-400 will be
deprecated in the future.
Change-Id: I3ccd0eb7b062922d2e4a374ff8c21e79fa357556
Vikram Kanigiri
committed
on 16 Mar 2015
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2015-03-10 |
User guide: Add dependency on libssl-dev for cert_create tool
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The 'libssl-dev' package must be installed on the host to build the
certificate generation tool. This patch adds it to the list of
required tools in the User Guide.
Change-Id: I018381fb14b7c2d2bd6f2b7929aaad0571f7eb2e
Sandrine Bailleux
committed
on 10 Mar 2015
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2015-03-05 |
TBB: use SHA256 to generate the certificate signatures
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This patch replaces SHA1 by SHA256 in the 'cert_create' tool, so
certificate signatures are generated according to the NSA Suite B
cryptographic algorithm requirements.
Documentation updated accordingly.
Change-Id: I7be79e6b2b62dac8dc78a4f4f5006e37686bccf6
Juan Castillo
committed
on 5 Mar 2015
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2015-02-12 |
Export maximum affinity using PLATFORM_MAX_AFFLVL macro
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This patch removes the plat_get_max_afflvl() platform API
and instead replaces it with a platform macro PLATFORM_MAX_AFFLVL.
This is done because the maximum affinity level for a platform
is a static value and it is more efficient for it to be defined
as a platform macro.
NOTE: PLATFORM PORTS NEED TO BE UPDATED ON MERGE OF THIS COMMIT
Fixes ARM-Software/tf-issues#265
Change-Id: I31d89b30c2ccda30d28271154d869060d50df7bf
Soby Mathew
committed
on 12 Feb 2015
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2015-02-04 |
Fix model command line for legacy VE memory map
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The command line options specified in the User Guide to run the AEMv8 Base FVP
with the legacy VE memory map apply only when the model is configured to use GIC
v2.0. This patch adds the 'gicv3.gicv2-only=1' to the command line to ensure
that the right version of GIC is used.
Change-Id: I34c44e19fd42c29818b734ac8f6aa9bf97b4e891
Achin Gupta
committed
on 4 Feb 2015
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2015-02-03 |
Merge pull request #254 from achingupta/ag/v1.1-doc-updates
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Documentation for version 1.1
danh-arm
committed
on 3 Feb 2015
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TBB: Add documentation for Trusted Board Boot
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This patch updates the user-guide.md with the various build options related to
Trusted Board Boot and steps to build a FIP image which includes this
support. It also adds a trusted-board-boot.md which describes the scope and
design of this feature.
Change-Id: Ifb421268ebf7e06a135684c8ebb04c94835ce061
Achin Gupta
authored
on 25 Jan 2015
Juan Castillo
committed
on 3 Feb 2015
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Documentation for version 1.1
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Final updates to readme.md and change-log.md for ARM Trusted Firmware version
1.1. Also increment the version in the Makefile.
Change-Id: Ib001a6ec9a9c570985841d06f0ff80ed76c2996b
Achin Gupta
committed
on 3 Feb 2015
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2015-02-02 |
Merge pull request #253 from danh-arm/dh/deps-for-v1.1
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Move up dependency versions in user guide
danh-arm
committed
on 2 Feb 2015
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Move up dependency versions in user guide
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Move up the version numbers in the user guide of:
* DS-5 (to v5.20)
* EDK2 (to v2.1-rc0)
* Linux Kernel (to 1.3-Juno)
* Linaro file-system (to 14.12)
* Juno SCP binary (to 1.5.0-rc0 within board recovery image 0.10.1).
Also remove duplicate information that is available from the
ARM Connected Community website.
* Base FVP (to 6.2)
* Foundation FVP (to 9.1). Also update the name of the Foundation
FVP binary since it has changed since version 2.1.
Co-Authored-By: Dan Handley <dan.handley@arm.com>
Change-Id: I1cf2f2b1a3f1b997ac905a4ab440876d265698c0
Sandrine Bailleux
authored
on 14 Jan 2015
Dan Handley
committed
on 2 Feb 2015
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Miscellaneous doc fixes for v1.1
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Change-Id: Iaf9d6305edc478d39cf1b37c8a70ccdf723e8ef9
Sandrine Bailleux
committed
on 2 Feb 2015
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2015-01-30 |
Fix the Cortex-A57 reset handler register usage
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The CPU specific reset handlers no longer have the freedom
of using any general purpose register because it is being invoked
by the BL3-1 entry point in addition to BL1. The Cortex-A57 CPU
specific reset handler was overwriting x20 register which was being
used by the BL3-1 entry point to save the entry point information.
This patch fixes this bug by reworking the register allocation in the
Cortex-A57 reset handler to avoid using x20. The patch also
explicitly mentions the register clobber list for each of the
callee functions invoked by the reset handler
Change-Id: I28fcff8e742aeed883eaec8f6c4ee2bd3fce30df
Soby Mathew
committed
on 30 Jan 2015
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2015-01-28 |
TBB: add a platform specific function to validate the ROTPK
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This patch adds the function plat_match_rotpk() to the platform
porting layer to provide a Root Of Trust Public key (ROTPK)
verification mechanism. This function is called during the
Trusted Board Boot process and receives a supposed valid copy
of the ROTPK as a parameter, usually obtained from an external
source (for instance, a certificate). It returns 0 (success) if
that key matches the actual ROTPK stored in the system or any
other value otherwise.
The mechanism to access the actual ROTPK stored in the system
is platform specific and should be implemented as part of this
function. The format of the ROTPK is also platform specific
(to save memory, some platforms might store a hash of the key
instead of the whole key).
TRUSTED_BOARD_BOOT build option has been added to allow the user
to enable the Trusted Board Boot features. The implementation of
the plat_match_rotpk() funtion is mandatory when Trusted Board
Boot is enabled.
For development purposes, FVP and Juno ports provide a dummy
function that returns always success (valid key). A safe trusted
boot implementation should provide a proper matching function.
Documentation updated accordingly.
Change-Id: I74ff12bc2b041556c48533375527d9e8c035b8c3
Juan Castillo
authored
on 7 Jan 2015
Dan Handley
committed
on 28 Jan 2015
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