LuminaSensum/arm-trusted-firmware

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LuminaSensum / arm-trusted-firmware

2019-11-13	a011942 Browse files » Merge changes from topic "tegra-downstream-092319" into integration ... * changes: Tegra194: add macros for security carveout configuration registers Tegra194: add 'TEGRA_TMRUS_SIZE' macro Tegra194: Fix TEGRA186_SMMU_CTX_SIZE Tegra194: Dont run MCE firmware on Emulation Tegra194: remove GPU, MPCORE and PTC registers from streamid list Tegra194: Support SMC64 encoding for MCE calls Tegra194: Enable MCE driver Tegra194: enable SMMU Tegra194: add support for multiple SMMU devices Tegra194: add SMMU and mc_sid support Tegra194: psci: support for 64-bit TZDRAM base Tegra194: base commit for the platform Revert "Tegra: Add support for fake system suspend" Sandrine Bailleux authored on 13 Nov 2019 TrustedFirmware Code Review committed on 13 Nov 2019
2019-11-13	0efb83e Browse files » Merge "Fix white space errors + remove #if defined" into integration Sandrine Bailleux authored on 13 Nov 2019 TrustedFirmware Code Review committed on 13 Nov 2019
2019-11-12	9afe8cd Browse files » Coding guideline suggest not to use unsigned long ... `unsigned long` should be replaced to 1. `unsigned int` or `unsigned long long` - If fixed, based on the architecture AArch32 or AArch64 2. `u_register_t` - If it is supposed to be 32-bit wide in AArch32 and 64-bit wide in AArch64. Translation descriptors are always 32-bit wide, here `uint32_t` is used to describe the `exact size` of translation descriptors instead of `unsigned int` which guarantees minimum 32-bits Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I6a2af2e8b3c71170e2634044e0b887f07a41677e Deepika Bhavnani committed on 12 Nov 2019
	63b9627 Browse files » Merge "plat/arm: Re-enable PIE when RESET_TO_BL31=1" into integration Paul Beesley authored on 12 Nov 2019 TrustedFirmware Code Review committed on 12 Nov 2019
	87d35d9 Browse files » Merge "TF-A Documentation: Update Security Advisory TFV-5 (CVE-2017-15031)" into integration Paul Beesley authored on 12 Nov 2019 TrustedFirmware Code Review committed on 12 Nov 2019
	494d57e Browse files » Merge "Disable stack protection explicitly" into integration Paul Beesley authored on 12 Nov 2019 TrustedFirmware Code Review committed on 12 Nov 2019
	f60ad9b Browse files » Merge "n1sdp: setup multichip gic routing table" into integration Paul Beesley authored on 12 Nov 2019 TrustedFirmware Code Review committed on 12 Nov 2019
	415f67e Browse files » Merge changes from topic "gic600_multichip" into integration ... * changes: gic/gic600: add support for multichip configuration plat/arm/gicv3: add support for probing multiple GIC Redistributor frames Paul Beesley authored on 12 Nov 2019 TrustedFirmware Code Review committed on 12 Nov 2019
2019-11-11	6799a37 Browse files » n1sdp: setup multichip gic routing table ... N1SDP supports multichip configuration wherein n1sdp boards are connected over high speed coherent CCIX link, for now only dual-chip is supported. Whether or not multiple chips are present is dynamically probed by SCP firmware and passed on to TF-A, routing table will be set up only if multiple chips are present. Initialize GIC-600 multichip operation by overriding the default GICR frames with array of GICR frames and setting the chip 0 as routing table owner. Change-Id: Ida35672be4bbf4c517469a5b330548d75e593ff2 Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Manish Pandey authored on 14 Oct 2019 Vijayenthiran Subramaniam committed on 11 Nov 2019
2019-11-11	fcc337c Browse files » gic/gic600: add support for multichip configuration ... Add support to configure GIC-600's multichip routing table registers. Introduce a new gic600 multichip structure in order to support platforms to pass their GIC-600 multichip information such as routing table owner, SPI blocks ownership. This driver is currently experimental and the driver api may change in the future. Change-Id: Id409d0bc07843e271ead3fc2f6e3cb38b317878d Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Vijayenthiran Subramaniam committed on 11 Nov 2019
2019-11-07	133a5c6 Browse files » plat/arm: Re-enable PIE when RESET_TO_BL31=1 ... Earlier PIE support was enabled for all arm platforms when RESET_TO_BL31=1, but later on it was restricted only to FVP with patch SHA d4580d17 because of n1sdp platform. Now it has been verified that PIE does work for n1sdp platform also, so enabling it again for all arm platforms. Change-Id: I05ad4f1775ef72e7cb578ec9245cde3fbce971a5 Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Manish Pandey committed on 7 Nov 2019
2019-11-05	658cb07 Browse files » mediatek: mt8183: switch PLL/CLKSQ/ck_off/axi_26m control to SPM ... 1. Switch ARMPLL_LL/CCIPLL/MAINPLL/MPLL control to SPM 2. Switch CLKSQ1/TDCLKSQ control to SPM 3. Switch ck_off/axi_26m control to SPM BUG=b:136980838 TEST=system suspend/resume passed Change-Id: I5c8506f7cf16d5cdaeb5ef8caa60a2992a361e18 Signed-off-by: Roger Lu <roger.lu@mediatek.com> Roger Lu authored on 28 Oct 2019 kenny liang committed on 5 Nov 2019
2019-11-05	74c2124 Browse files » plat/arm/gicv3: add support for probing multiple GIC Redistributor frames ... ARM platform can have a non-contiguous GICR frames. For instance, a multi socket platform can have two or more GIC Redistributor frames which are 4TB apart. Hence it is necessary for the `gicv3_rdistif_probe` function to probe all the GICR frames available in the platform. Introduce `plat_arm_override_gicr_frames` function which platforms can use to override the default gicr_frames which holds the GICR base address of the primary cpu. Change-Id: I1f537b0d871a679cb256092944737f2e55ab866e Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Vijayenthiran Subramaniam committed on 5 Nov 2019
2019-11-04	c605ecd Browse files » TF-A Documentation: Update Security Advisory TFV-5 (CVE-2017-15031) ... This patch updates description of Security Advisory TFV-5. Change-Id: Ieaee0b51a79843345b1aca5d0e20c4964beb3c95 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com> Alexei Fedorov committed on 4 Nov 2019
2019-11-04	d69f998 Browse files » Merge "SMMUv3:Changed retry loop to delay timer(GENFW-3329)" into integration Alexei Fedorov authored on 4 Nov 2019 TrustedFirmware Code Review committed on 4 Nov 2019
2019-11-01	620dd58 Browse files » SMMUv3:Changed retry loop to delay timer(GENFW-3329) ... Instead of retry polling, timer of 1ms is used to poll Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I7e028dc68138d2888e3cf0cbed744f5e6bc6ff42 Deepika Bhavnani committed on 1 Nov 2019
2019-10-31	1d2b416 Browse files » Merge changes I75799fd4,I4781dc6a into integration ... * changes: n1sdp: update platform macros for dual-chip setup n1sdp: introduce platform information SDS region Paul Beesley authored on 31 Oct 2019 TrustedFirmware Code Review committed on 31 Oct 2019
2019-10-31	f91a8e4 Browse files » n1sdp: update platform macros for dual-chip setup ... N1SDP supports multichip configuration wherein n1sdp boards are connected over high speed coherent CCIX link for now only dual-chip is supported. A single instance of TF-A runs on master chip which should be aware of slave chip's CPU and memory topology. This patch updates platform macros to include remote chip's information and also ensures that a single version of firmware works for both single and dual-chip setup. Change-Id: I75799fd46dc10527aa99585226099d836c21da70 Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Manish Pandey committed on 31 Oct 2019
2019-10-30	34c7af4 Browse files » n1sdp: introduce platform information SDS region ... Platform information structure holds information about platform's DDR size(local/remote) which will be used to zero out the memory before enabling the ECC capability as well as information about multichip setup. Multichip and remote DDR information can only be probed in SCP, SDS region will be used by TF-A to get this information at boot up. This patch introduces a new SDS to store platform information, which is populated dynamically by SCP Firmware.previously used mem_info SDS is also made part of this structure itself. The platform information is also passed to BL33 by copying it to Non- Secure SRAM. Change-Id: I4781dc6a7232c3c0a3219b164d943ce9e3e469ee Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Manish Pandey committed on 30 Oct 2019
2019-10-30	5d71d3f Browse files » Merge "doc: Fix syntax erros in I/O storage layer plantuml diagrams" into integration Paul Beesley authored on 30 Oct 2019 TrustedFirmware Code Review committed on 30 Oct 2019
2019-10-29	cc76d67 Browse files » Merge "ti: k3: common: Add PIE support" into integration Sandrine Bailleux authored on 29 Oct 2019 TrustedFirmware Code Review committed on 29 Oct 2019
2019-10-29	ff835a9 Browse files » ti: k3: common: Add PIE support ... Running TF-A from non-standard location such as DRAM is useful for some SRAM heavy use-cases. Allow the TF-A binary to be executed from an arbitrary memory location. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: Icd97926e4d97f37d7cde4a92758a52f57d569111 Andrew F. Davis committed on 29 Oct 2019
2019-10-28	ec477e7 Browse files » doc: Fix syntax erros in I/O storage layer plantuml diagrams ... Some of the plantuml diagrams in the I/O storage abstraction layer documentation are absent from the rendered version of the porting guide. The build log (see [1] for example) reports a syntax error in these files. This is due to the usage of the 'order' keyword on the participants list, which does not seem to be supported by the version of plantuml installed on the ReadTheDocs server. Fix these syntax errors by removing the 'order' keyword altogether. We simply rely on the participants being declared in the desired order, which will be the order of display, according to the plantuml documentation. [1] https://readthedocs.org/api/v2/build/9870345.txt Change-Id: Ife35c74cb2f1dac28bda07df395244639a8d6a2b Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Sandrine Bailleux committed on 28 Oct 2019
2019-10-25	a74e3a1 Browse files » Merge "plat/arm: use Aff3 bits also to validate mpidr" into integration Alexei Fedorov authored on 25 Oct 2019 TrustedFirmware Code Review committed on 25 Oct 2019
2019-10-24	3b2b337 Browse files » Tegra194: add macros for security carveout configuration registers ... This patch adds macros defining the generalised security carveout registers. These macros help us program the TZRAM carveout access and the Video Protect Clear carveout access. Change-Id: I8f7b24b653fdb702fb57a4097801cb3eae050294 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Varun Wadekar committed on 24 Oct 2019
	d82f5a3 Browse files » Tegra194: add 'TEGRA_TMRUS_SIZE' macro ... This patch defines the macro for the TEGRA_TMRUS aperture size. Change-Id: I33fb674c6a7be8d02971667e7bf8650b7adc62ef Signed-off-by: Steven Kao <skao@nvidia.com> Steven Kao authored on 7 Mar 2017 Varun Wadekar committed on 24 Oct 2019
	ddbf946 Browse files » Tegra194: Fix TEGRA186_SMMU_CTX_SIZE ... TEGRA186_SMMU_CTX_SIZE should match the numbe of elements in smmu_ctx_regs, which is defined in smmu_plat_config.h. The current number of elements are 0x490. Change-Id: If0614ea8ef8b6a8f5da1a3279abaf9255eb76420 Signed-off-by: Stefan Kristiansson <stefank@nvidia.com> Stefan Kristiansson authored on 20 Mar 2017 Varun Wadekar committed on 24 Oct 2019
	4fb71ea Browse files » Tegra194: Dont run MCE firmware on Emulation ... Dont run MCE firmware on pre-silicon emulation platforms Change-Id: I2a8d653e46f494621580ca92271a18e62f648859 Signed-off-by: Rohit Khanna <rokhanna@nvidia.com> Rohit Khanna authored on 3 Mar 2017 Varun Wadekar committed on 24 Oct 2019
	e9bb627 Browse files » Tegra194: remove GPU, MPCORE and PTC registers from streamid list ... GPU, MPCORE and PTC clients are changed and not going through SMMU. Removing it from streamid list. Change-Id: I14b450a11f02ad6c1a97e67e487d6d624911d019 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Pritesh Raithatha authored on 13 Feb 2017 Varun Wadekar committed on 24 Oct 2019
	7e4ffcd Browse files » Tegra194: Support SMC64 encoding for MCE calls ... This patch uses SMC64 encoding for all MCE SMC calls originating from the linux kernel. Change-Id: Ic4633de5c638566012db033bbaf8c9d9343acdc0 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Varun Wadekar committed on 24 Oct 2019