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2019-12-13	2bcc672 Browse files » Merge changes from topic "aa/sel2_support" into integration ... * changes: S-EL2 Support: Check for AArch64 Add support for enabling S-EL2 Olivier Deprez authored on 13 Dec 2019 TrustedFirmware Code Review committed on 13 Dec 2019
2019-12-12	7999904 Browse files » Merge "PIE: make call to GDT relocation fixup generalized" into integration Soby Mathew authored on 12 Dec 2019 TrustedFirmware Code Review committed on 12 Dec 2019
2019-12-12	da90359 Browse files » PIE: make call to GDT relocation fixup generalized ... When a Firmware is complied as Position Independent Executable it needs to request GDT fixup by passing size of the memory region to el3_entrypoint_common macro. The Global descriptor table fixup will be done early on during cold boot process of primary core. Currently only BL31 supports PIE, but in future when BL2_AT_EL3 will be compiled as PIE, it can simply pass fixup size to the common el3 entrypoint macro to fixup GDT. The reason for this patch was to overcome the bug introduced by SHA 330ead806 which called fixup routine for each core causing re-initializing of global pointers thus overwriting any changes done by the previous core. Change-Id: I55c792cc3ea9e7eef34c2e4653afd04572c4f055 Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Manish Pandey committed on 12 Dec 2019
2019-12-11	fcccd35 Browse files » Merge "libc: add memrchr" into integration Alexei Fedorov authored on 11 Dec 2019 TrustedFirmware Code Review committed on 11 Dec 2019
2019-12-11	ebff107 Browse files » libc: add memrchr ... This function scans a string backwards from the end for the first instance of a character. Change-Id: I46b21573ed25a0ff222eac340e1e1fb93b040763 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Ambroise Vincent authored on 19 Jun 2019 Olivier Deprez committed on 11 Dec 2019
2019-12-10	9be5ca7 Browse files » Merge "arm: Fix current RECLAIM_INIT_CODE behavior" into integration Sandrine Bailleux authored on 10 Dec 2019 TrustedFirmware Code Review committed on 10 Dec 2019
2019-12-09	a71c59d Browse files » arm: Fix current RECLAIM_INIT_CODE behavior ... Previously the .init section was created even when the reclaim flag was manually set to 0. Change-Id: Ia9e7c7997261f54a4eca725d7ea605192f60bcf8 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Zelalem Aweke <zelalem.aweke@arm.com> Ambroise Vincent authored on 16 Jul 2019 Zelalem committed on 9 Dec 2019
2019-12-06	db3ae85 Browse files » S-EL2 Support: Check for AArch64 ... Check that entry point information requesting S-EL2 has AArch64 as an execution state during context setup. Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com> Change-Id: I447263692fed6e55c1b076913e6eb73b1ea735b7 Artsem Artsemenka committed on 6 Dec 2019
	0376e7c Browse files » Add support for enabling S-EL2 ... This patch adds support for enabling S-EL2 if this EL is specified in the entry point information being used to initialise a secure context. It is the caller's responsibility to check if S-EL2 is available on the system before requesting this EL through the entry point information. Signed-off-by: Achin Gupta <achin.gupta@arm.com> Change-Id: I2752964f078ab528b2e80de71c7d2f35e60569e1 Achin Gupta authored on 11 Oct 2019 Artsem Artsemenka committed on 6 Dec 2019
	ade3f5d Browse files » Merge changes from topic "bs/libc" into integration ... * changes: libc: Consolidate the size_t and NULL definitions libc: Consolidate unified definitions libc: Unify intmax_t and uintmax_t on AArch32/64 Soby Mathew authored on 6 Dec 2019 TrustedFirmware Code Review committed on 6 Dec 2019
	d45c323 Browse files » libc: Consolidate the size_t and NULL definitions ... Consolidate the definition of size_t to one header per AArch, and the definition of NULL to one header Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com> Change-Id: Iecfbad2cf360cfb705ce7aaa981700fd16219b82 Bence Szépkúti committed on 6 Dec 2019
	b382ac6 Browse files » libc: Consolidate unified definitions ... As supporting architectures aside from AArch32 and AArch64 is not a concern, keeping identical definitions in two places for a large part of the libc seems counterproductive The int128 types were left un-unified as __int128 is not supported by gcc on AArch32 Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com> Change-Id: Idf08e6fab7e4680d9da62d3c57266ea2d80472cf Bence Szépkúti committed on 6 Dec 2019
	d005cfb Browse files » libc: Unify intmax_t and uintmax_t on AArch32/64 ... Conceptually, these are supposed to be the largest integers representable in C, but GCC and Clang define them as long long for compatibility. Signed-off-by: Bence Szépkúti <bence.szepkuti@arm.com> Change-Id: I7c0117f3be167342814d260a371889120dcf6576 Bence Szépkúti committed on 6 Dec 2019
2019-11-26	e34cc0c Browse files » Changes to support updated register usage in SMCCC v1.2 ... From AArch64 state, arguments are passed in registers W0-W7(X0-X7) and results are returned in W0-W7(X0-X7) for SMC32(SMC64) calls. From AArch32 state, arguments are passed in registers R0-R7 and results are returned in registers R0-R7 for SMC32 calls. Most of the functions and macros already existed to support using upto 8 registers for passing/returning parameters/results. Added few helper macros for SMC calls from AArch32 state. Link to the specification: https://developer.arm.com/docs/den0028/c Change-Id: I87976b42454dc3fc45c8343e9640aa78210e9741 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Madhukar Pappireddy committed on 26 Nov 2019
2019-11-12	63b9627 Browse files » Merge "plat/arm: Re-enable PIE when RESET_TO_BL31=1" into integration Paul Beesley authored on 12 Nov 2019 TrustedFirmware Code Review committed on 12 Nov 2019
2019-11-11	fcc337c Browse files » gic/gic600: add support for multichip configuration ... Add support to configure GIC-600's multichip routing table registers. Introduce a new gic600 multichip structure in order to support platforms to pass their GIC-600 multichip information such as routing table owner, SPI blocks ownership. This driver is currently experimental and the driver api may change in the future. Change-Id: Id409d0bc07843e271ead3fc2f6e3cb38b317878d Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Vijayenthiran Subramaniam committed on 11 Nov 2019
2019-11-07	133a5c6 Browse files » plat/arm: Re-enable PIE when RESET_TO_BL31=1 ... Earlier PIE support was enabled for all arm platforms when RESET_TO_BL31=1, but later on it was restricted only to FVP with patch SHA d4580d17 because of n1sdp platform. Now it has been verified that PIE does work for n1sdp platform also, so enabling it again for all arm platforms. Change-Id: I05ad4f1775ef72e7cb578ec9245cde3fbce971a5 Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Manish Pandey committed on 7 Nov 2019
2019-11-05	74c2124 Browse files » plat/arm/gicv3: add support for probing multiple GIC Redistributor frames ... ARM platform can have a non-contiguous GICR frames. For instance, a multi socket platform can have two or more GIC Redistributor frames which are 4TB apart. Hence it is necessary for the `gicv3_rdistif_probe` function to probe all the GICR frames available in the platform. Introduce `plat_arm_override_gicr_frames` function which platforms can use to override the default gicr_frames which holds the GICR base address of the primary cpu. Change-Id: I1f537b0d871a679cb256092944737f2e55ab866e Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Vijayenthiran Subramaniam committed on 5 Nov 2019
2019-10-11	89632e6 Browse files » Replace deprecated __ASSEMBLY__ macro with __ASSEMBLER__ ... Change-Id: I497072575231730a216220f84a6d349a48eaf5e3 Signed-off-by: Balint Dobszay <balint.dobszay@arm.com> Balint Dobszay committed on 11 Oct 2019
2019-10-08	9d811b8 Browse files » delay: correct timeout_init_us() ... The function has to use read_cntpct_el0() to update the counter, and not read_cntfrq_el0(). Change-Id: I9c676466e784c3122e9ffc2d87e66708797086e7 Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier committed on 8 Oct 2019
2019-10-07	80003d8 Browse files » Merge "Explicitly disable the SPME bit in MDCR_EL3" into integration Soby Mathew authored on 7 Oct 2019 TrustedFirmware Code Review committed on 7 Oct 2019
	25792ce Browse files » Merge "Neoverse N1 Errata Workaround 1542419" into integration Soby Mathew authored on 7 Oct 2019 TrustedFirmware Code Review committed on 7 Oct 2019
	2a7adf2 Browse files » Explicitly disable the SPME bit in MDCR_EL3 ... Currently the MDCR_EL3 initialisation implicitly disables MDCR_EL3.SPME by using mov_imm. This patch makes the SPME bit more visible by explicitly disabling it and documenting its use in different versions of the architecture. Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com> Change-Id: I221fdf314f01622f46ac5aa43388f59fa17a29b3 Petre-Ionut Tudor committed on 7 Oct 2019
2019-10-04	8094262 Browse files » Neoverse N1 Errata Workaround 1542419 ... Coherent I-cache is causing a prefetch violation where when the core executes an instruction that has recently been modified, the core might fetch a stale instruction which violates the ordering of instruction fetches. The workaround includes an instruction sequence to implementation defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap handler to execute a TLB inner-shareable invalidation to an arbitrary address followed by a DSB. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6 laurenw-arm authored on 20 Aug 2019 Deepika Bhavnani committed on 4 Oct 2019
2019-10-03	0711ee5 Browse files » delay: timeout detection support ... Introduce timeout_init_us/timeout_elapsed() delay tracking with CNTPCT. timeout_init_us(some_timeout_us); returns a reference to detect timeout for the provided microsecond delay value from current time. timeout_elapsed(reference) return true/false whether the reference timeout is elapsed. Cherry picked from OP-TEE implementation [1]. [1] commit 33d30a74502b ("core: timeout detection support") Minor: - Remove stm32mp platform duplicated implementation. - Add new include in marvell ble.mk Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: Iaef6d43c11a2e6992fb48efdc674a0552755ad9c Lionel Debieve committed on 3 Oct 2019
	78f02ae Browse files » Introducing support for Cortex-A65AE ... Change-Id: I1ea2bf088f1e001cdbd377cbfb7c6a2866af0422 Signed-off-by: Imre Kis <imre.kis@arm.com> Imre Kis committed on 3 Oct 2019
	2d35bc1 Browse files » Merge changes from topic "stm32mp_corrections_w40" into integration ... * changes: gpio: stm32_gpio: do not mix error code types fdts: stm32mp1: move FDCAN to PLL4_R mmc: increase delay between ACMD41 retries crypto: stm32_hash: align stm32_hash_update() prototype Soby Mathew authored on 3 Oct 2019 TrustedFirmware Code Review committed on 3 Oct 2019
	34c4f86 Browse files » Merge "Add missing support for BL2_AT_EL3 in XIP memory" into integration Soby Mathew authored on 3 Oct 2019 TrustedFirmware Code Review committed on 3 Oct 2019
	19e2af7 Browse files » crypto: stm32_hash: align stm32_hash_update() prototype ... Use size_t for length parameter in header file, as in .c file. Change-Id: I310f2a6159cde1c069b4f814f6558c2488c203ec Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier committed on 3 Oct 2019
2019-10-02	6ad216d Browse files » Introducing support for Cortex-A65 ... Change-Id: I645442d52a295706948e2cac88c36c1a3cb0bc47 Signed-off-by: Imre Kis <imre.kis@arm.com> Imre Kis committed on 2 Oct 2019