Merge pull request #1540 from MISL-EBU-System-SW/marvell-updates-18.09 ...

Marvell updates 18.09

fix: tools: Fix doimage syntax breaking secure mode build ...

Missing ")" in fprintf causing build break in secure boot mode.

Change-Id: Ice555571683b68bb0d81479e9fc8abc4296809ac
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

plat: marvell: Update Marvell base code version to 18.09.1 ...

Change-Id: I908844364bf8080612aaa6d750d7d2441ecc2eb8
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

plat: svc: ap807: add SVC configuration for AP807 ...

- add svc configuration according to values burnt
  to the chip efuse

Change-Id: Icf5d7cc41bc09ac2244d0a126106e681afebb064
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

tools: doimage: Add secure image key file examples ...

Add example keys for building trusted flash images using
doimage tools.
Similar files can be generated using openssl or mbedtls.
Marvell platform make files are using trusted boot
configurations from this example etst vector.

Change-Id: I38a2e295171bee4c14005ce6f020b352c683496e
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

fix: marvell: Check the required libraries before building doimage ...

Some customers are missing host libraries required for doimage
builds.
This patch requests for the library installation check for every
doimage build and suggest the required installation steps in case
of missing headers.

Change-Id: Icde18c3d4d6045f65e50d2dc9e6514971f40033e
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>

plat: a8k: enable PMU overflow interrupt handler ...

This patch enables handling PMU overflow IRQ by GIC SPI's
directly in EL3. Also implement additional SMC routine,
which can disable the solution on demand in runtime.

Since it is possible to configure PMU interrupt trigger type
in the MADT ACPI table, it is enough to set it only once in EL3
during initialization.

Change-Id: Ie76aa62ccc4fd7cabfec9e3d5ed9970ada1c1b2a
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

marvell: drivers: correct RTC init sequence ...

It turned out that resetting the RTC time register is not
necessary during initial configuration. Safely remove it
from the sequence.

Change-Id: Id2b9c7db44a8c8dbe88a7f8a21695b72a7fd78ee
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Nadav Haklai <nadavh@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

gicv2: enable configuring IRQ trigger type ...

This patch introduces new helper routines that allow
configuring the individual IRQs to be edge/level-triggered
via GICD_ICFGR registers. This is helpful to modify
the default configuration of the non-secure GIC SPI's, which
are all set during initialization to be level-sensitive.

Change-Id: I23deb4a0381691a686a3cda52405aa1dfd5e56f2
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

Merge pull request #1484 from nathan-menhorn/tee-validate-header-603 ...

Update optee_utils.c to fix ARM-software/tf-issues#603

Merge pull request #1541 from rajanv-xilinx/integration-num-clocks ...

zynqmp: pm: Add API to get number of clocks

Merge pull request #1551 from glneo/k3-pwr-down-psci ...

Add PSCI core power down for K3

marvell: pm: do not panic by default in cpu_standby ...

Current default behavior of cpu_standby callback
is problematic during the SBSA test, which is
unable to run due to EL3 panic. Make it dependent on
the PM firmware running.

Change-Id: I7a53de8c880bd23b157dd65ce14bb48b5a5c76c8
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

mvebu: cp110: fix spelling in register definition ...

Use PF instead of PP post-fix, since it is referring to "Phase Final"
(only G3 related register had correct spelling for relevant bit).

Change-Id: Ia5a9c9c78b74b15f7f8adde2c3ef4784c513da2c
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

mvebu: cp110: align all comphy_index arguments type ...

The biggest comphy index can be equal to 6 so there is no need to use
uint64_t for storing it.

Change-Id: I14c2b68e51678a560815963c72aed0c37068f926
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

plat: marvell: a80x0: reconfigure CP0 PCIE0 windows ...

In order to allow the use of PCIe cards such as graphics cards, whose
demands for BAR space are typically much higher than those of network
or SATA/USB cards, reconfigure the I/O windows so we can declare two
MMIO PCI regions: a 512 MB MMIO32 one at 0xc000_0000 and a 4 GB MMIO64
one at 0x8_0000_0000. In addition, this will leave ample room for an
ECAM config space at 0xe000_0000 (up to the ECAM maximum of 256 MB)

For compatibility with older kernels or firmware, leave the original
16 MB window in place as well.

Change-Id: Ia8177194e542078772f90941eced81b231c16887
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

plat: marvell: a70x0: reconfigure CP0 PCIE2 windows ...

In order to allow the use of PCIe cards such as graphics cards, whose
demands for BAR space are typically much higher than those of network
or SATA/USB cards, reconfigure the I/O windows so we can declare two
MMIO PCI regions: a 512 MB MMIO32 one at 0xc000_0000 and a 4 GB MMIO64
one at 0x8_0000_0000. In addition, this will leave ample room for an
ECAM config space at 0xe000_0000 (up to the ECAM maximum of 256 MB)

For compatibility with older kernels or firmware, leave the original
16 MB window in place as well.

Change-Id: I80b00691ae8d0a3f3f7285b8e0bfc21c0a095e94
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

a8k: use the memory controller feature to protect the RT service region ...

Define the RT service space as secure with use of memory controller
trustzone feature. Thanks to this protection, any NS-Bootloader nor NS-OS,
won't be able to access RT services (e.g. accidentally overwrite it,
which will at best result in RT services unavailability).

Change-Id: Ie5b6cbe9a1b77879d6d8f8eac5d4e41e468496ce
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

drivers: marvell: mc_trustzone: add driver for mc trustzone ...

Add simple driver which allows to configure the memory controller trust
zones. It is responsible for opening mc trustzone window, with
appropriate base address, size and attributes.

Example of usage in upcoming commits.

Change-Id: I8bea17754d31451b305040ee7de331fb8db0c63f
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

plat: marvell: rename common include file ...

Rename a8k_common.h to armada_common.h to keep the same header
name across all other Marvell Armada platforms.
This is especially useful since various Marvell platforms may
use common platform files and share the driver modules.

Change-Id: I7262105201123d54ccddef9aad4097518f1e38ef
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

docs: marvell: Update build manual ...

Update build manual
- remove irrelevant platforms and environemnt variables
- add links to BLE and mv_ddr Github repositories

Change-Id: Ie389c61f014751cdc0459b3f78c70ede694d27b8
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

ti: k3: common: Add basic PSCI core off support ...

Use TI-SCI messages to request core power down from system controller
firmware.

Signed-off-by: Andrew F. Davis <afd@ti.com>

Merge pull request #1552 from glneo/build-fix ...

GIC: Fix build error

Merge pull request #1547 from semihalf-dabros-jan/semihalf-dabros-jan/fix_errmisc ...

AARCH64: Fix credentials for ERXMISC0_EL1 and ERXMISC1_EL1

Merge pull request #1550 from danielboulby-arm/db/weakdefs ...

Prevent two weak definitions of the same function

Merge pull request #1549 from danielboulby-arm/db/pointer ...

Remove rt_svc_descs pointer from global scope

GIC: Fix build error ...

Pointers should be comparied to NULL.

Fixes: 3fea9c8b8e8e ("gic: Fix types")
Signed-off-by: Andrew F. Davis <afd@ti.com>

Prevent two weak definitions of the same function ...

Add another level of abstraction of weak defs for
arm_bl2_handle_post_image_load to prevent two weak definitions
of the same function

Change-Id: Ie953786f43b0f88257c82956ffaa5fe0d19603db
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

Remove rt_svc_descs pointer from global scope ...

A pointer to rt_svc_desc_t is defined both in the function
handle_runtime_svc() and globally. Since the value of the
pointer RT_SVC_DESCS_START is defined by the linker and
never changes make this definition local in both
handle_runtime_svc() and runtime_svc_init() to reduce the
number of loads

Change-Id: Iea42c778d8599a26c87700009163b5a8d7d60be2
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

Merge pull request #1546 from antonio-nino-diaz-arm/an/log-misra ...

Fix some MISRA defect in log helpers