Merge "dtsi: Update the nv-counter node in the device tree" into integration

Merge changes from topic "tegra-downstream-08282020" into integration ...

* changes:
  Tegra: common: disable GICC after domain off
  cpus: denver: skip DCO enable/disable for recent SKUs

Merge "Remove Jack Bond-Preston as CMake Build Definitions code owner" into integration

Merge "Add support to export a /cpus node to the device tree." into integration

Add support to export a /cpus node to the device tree. ...

This patch creates and populates the /cpus node in a device tree
based on the existing topology. It uses the minimum required nodes
and properties to satisfy the binding as specified in
https://www.kernel.org/doc/Documentation/devicetree/bindings/arm/cpus.txt

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I03bf4e9a6427da0a3b8ed013f93d7bc43b5c4df0

Merge "sp_min: Avoid platform security reconfiguration" into integration

Merge "doc: Update the cot-binding for nv-counter node" into integration

Merge changes from topic "tegra-downstream-08282020" into integration ...

* changes:
  Tegra: platform specific BL31_SIZE
  Tegra186: sanity check power state type
  Tegra: fixup CNTPS_TVAL_EL1 delay timer reads
  Tegra: add platform specific 'runtime_setup' handler
  Tegra: remove ENABLE_SVE_FOR_NS = 0
  lib: cpus: denver: add MIDR PN9 variant
  cpus: denver: introduce macro to declare cpu_ops

Tegra: common: disable GICC after domain off ...

The the GIC CPU interface should be disabled after cpu off. The
Tegra power management code should mark the connected core as asleep
as part of the CPU off sequence.

This patch disables the GICC after CPU off as a result.

Signed-off-by: anzhou <anzhou@nvidia.com>
Change-Id: Ib1a3d8903f5e6d55bd2ee0c16134dbe2562235ea

cpus: denver: skip DCO enable/disable for recent SKUs ...

DCO is not supported by the SKUs released after MIDR_PN4. This
patch skips enabling or disabling the DCO on these SKUs.

Change-Id: Ic31a829de3ae560314d0fb5c5e867689d4ba243b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: platform specific BL31_SIZE ...

This patch moves the BL31_SIZE to the Tegra SoC specific
tegra_def.h. This helps newer platforms configure the size of
the memory available for BL31.

Signed-off-by: anzhou <anzhou@nvidia.com>
Change-Id: I43c60b82fa7e43d5b05d87fbe7d673d729380d82

Tegra186: sanity check power state type ...

This patch sanity checks the power state type before use,
from the platform's PSCI handler.

Verified with TFTF Standard Test Suite.

Change-Id: Icd45faac6c023d4ce7f3597b698d01b91a218124
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: fixup CNTPS_TVAL_EL1 delay timer reads ...

The delay_timer driver for Tegra uses the CNTPS_TVAL_EL1 secure, physical,
decrementing timer as the source. The current logic incorrectly marks this
as an incrementing timer, by negating the timer value.

This patch fixes the anomaly and updates the driver to remove this logic.

Signed-off-by: anzhou <anzhou@nvidia.com>
Change-Id: I60490bdcaf0b66bf4553a6de3f4e4e32109017f4

Tegra: add platform specific 'runtime_setup' handler ...

Tegra SoCs would like the flexibility to perform chip specific actions
before we complete cold boot. This patch introduces a platform specific
'runtime_setup' handler to provide that flexibility.

Change-Id: I13b2489f631f775cae6f92acf51a240cd036ef11
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>

Tegra: remove ENABLE_SVE_FOR_NS = 0 ...

The SVE CPU extension library reads the id_aa64pfr0_el1 register to
check if SVE is enabled. Tegra platforms disabled ENABLE_SVE_FOR_NS for
pre-8.2 platforms, but this flag can safely be enabled now that the
library can enable the feature at runtime.

This patch updates the makefile to remove "ENABLE_SVE_FOR_NS = 0"
as a result.

Change-Id: Ia2a89ac90644f8c0d39b41d321e04458ff6be6e1
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>

lib: cpus: denver: add MIDR PN9 variant ...

This patch introduces support for PN9 variant for some
Denver based platforms.

Original change by: Hemant Nigam <hnigam@nvidia.com>

Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
Change-Id: I331cd3a083721fd1cd1b03f4a11b32fd306a21f3

cpus: denver: introduce macro to declare cpu_ops ...

This patch introduces a macro to declare cpu_op for all Denver
SKUs.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ibcf88c3256fc5dcaa1be855749ebd2c5c396c977

Merge "qti: spmi_arb: Fix coverity integer conversion warnings" into integration

Merge changes from topic "tegra-downstream-08252020" into integration ...

* changes:
  Tegra194: remove unused tegra_mc_defs header
  Tegra: memctrl: platform setup handler functions
  Tegra194: memctrl: remove streamid security cfg registers
  Tegra194: memctrl: remove streamid override cfg registers
  Tegra: debug prints indicating SC7 entry sequence completion
  Tegra194: add strict checking mode verification
  Tegra194: memctrl: update TZDRAM base at 1MB granularity
  Tegra194: ras: split up RAS error clear SMC call.
  Tegra: platform specific GIC sources
  Tegra194: add memory barriers during DRAM to SysRAM copy
  Tegra: sip: add VPR resize enabled check
  Tegra194: add redundancy checks for MMIO writes
  Tegra: remove unused cortex_a53.h
  Tegra194: report failure to enable dual execution
  Tegra194: verify firewall settings before resource use

Merge changes from topic "tc0/dts" into integration ...

* changes:
  fdts: tc0: add support for cpu-idle-states
  fdts: tc0: Add node for mmc

Remove Jack Bond-Preston as CMake Build Definitions code owner ...

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I542ec3cf1bb929a5656dda6dbad816b69837c646

sp_min: Avoid platform security reconfiguration ...

In the case of Juno AArch32, platform security configuration
gets done from both BL2 and SP_MIN(BL32) components when
JUNO_AARCH32_EL3_RUNTIME and RESET_TO_SP_MIN build options
are set.
Fix is provided to avoid Platform security configuration from
SP_MIN when it is already done in BL2.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I702e91dacb4cdd2d10e339ddeaea91289bef3229

dtsi: Update the nv-counter node in the device tree ...

Created a header file defining the id of the various nv-counters
used in the system.
Also, updated the device tree to add 'id' property for the trusted
and non-trusted nv-counters.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ia41a557f7e56ad4ed536aee11c7a59e078ae07c0

doc: Update the cot-binding for nv-counter node ...

Updated the cot-binding documentation to add 'id'
property for the trusted and non-trusted nv-counters.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: If1c628c5b90fe403dd96c7cd0cd04f37288c965c

Tegra194: remove unused tegra_mc_defs header ...

This patch removes the unused header from the Tegra194
platform files. As a result, the TSA MMIO would be
removed from the memory map too.

Change-Id: I2d38b3da7a119f5dfd6cfd429e481f4e6ad3481e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: memctrl: platform setup handler functions ...

The driver initially contained the setup steps to help Tegra186
and Tegra194 SoCs. In order to support future SoCs and make sure
that the driver remains generic enough, some code should be moved
to SoC.

This patch creates a setup handler for a platform to implement its
initialization sequence.

Change-Id: I8bab7fd07f25e0457ead8e2d2713efe54782a59b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra194: memctrl: remove streamid security cfg registers ...

The stream ID security configuration settings shall be done by the
previous level bootloader. This change removes the same settings
from the Tegra194 platform code as a result.

Change-Id: Ia170ca4c2119db8f1d0251f1c193add006f81004
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

Tegra194: memctrl: remove streamid override cfg registers ...

The stream ID override configuration is saved during System Suspend
as part MB1 bct. This change removes the same support from the Tegra194
platform code as a result.

Change-Id: I4c19dc0d8b29190908673fb5ed7ed892af8906ab
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

Tegra: debug prints indicating SC7 entry sequence completion ...

This patch adds prints to display the completion of System Suspend
programming sequence for Tegra platforms. The console needs to
be kept alive until the very end of the System Suspend sequence as
a result.

Change-Id: I8e0e2054a272665d0a067bb894dda1605a9d2eb7
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra194: add strict checking mode verification ...

After enabling the strict checking mode, verify that
the strict mode has really been enabled by querying
the MCE.

If the mode is found to be disabled, the code should
assert.

Change-Id: I113ec8decb737f8208059a2a3ba3076fad77890e
Signed-off-by: Anthony Zhou <anzhou@nvidia.com>