Juno: Introduce juno_getentropy(void *buf, size_t len) ...

This function fills the buffer (first argument) with the specified
number of bytes (second argument) from the trusted entropy source.

This function will be used to initialize the stack protector canary.

Change-Id: Iff15aaf4778c13fa883ecb5528fcf9b8479d4489
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>

Introduce MIN()/MAX() macros in utils.h ...

Change-Id: If88270bc9edb32634a793b1e1be6c4829f39b9c5
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>

Add support for GCC stack protection ...

Introduce new build option ENABLE_STACK_PROTECTOR. It enables
compilation of all BL images with one of the GCC -fstack-protector-*
options.

A new platform function plat_get_stack_protector_canary() is introduced.
It returns a value that is used to initialize the canary for stack
corruption detection. Returning a random value will prevent an attacker
from predicting the value and greatly increase the effectiveness of the
protection.

A message is printed at the ERROR level when a stack corruption is
detected.

To be effective, the global data must be stored at an address
lower than the base of the stacks. Failure to do so would allow an
attacker to overwrite the canary as part of an attack which would void
the protection.

FVP implementation of plat_get_stack_protector_canary is weak as
there is no real source of entropy on the FVP. It therefore relies on a
timer's value, which could be predictable.

Change-Id: Icaaee96392733b721fa7c86a81d03660d3c1bc06
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>

Remove dead loops in assert() in C and ASM ...

The desired behaviour is to call `plat_panic_handler()`, and to use
`no_ret` to do so from ASM.

Change-Id: I88b2feefa6e6c8f9bf057fd51ee0d2e9fb551e4f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Flush console where necessary ...

Call console_flush() before execution either terminates or leaves an
exception level.

Fixes: ARM-software/tf-issues#123

Change-Id: I64eeb92effb039f76937ce89f877b68e355588e3
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Add and use plat_crash_console_flush() API ...

This API makes sure that all the characters sent to the crash console
are output before returning from it.

Porting guide updated.

Change-Id: I1785f970a40f6aacfbe592b6a911b1f249bb2735
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Add console_core_flush() in upstream platforms ...

It is needed to add placeholders for this function because, as this is
not a `plat_xxx()` function, there aren't weak definitions of it in any
file.

If `console_flush()` is used and there isn't an implementation of
`console_core_flush()` in any file, the compilation will fail.

Change-Id: I50eb56d085c4c9fbc85d40c343e86af6412f3020
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Add console_flush() to console API ...

This function ensures that console output is flushed, for example
before shutting down or use by another component

In line with other console APIs, console_flush() wraps
console_core_flush().

Also implement console_core_flush() for PL011.

Change-Id: I3db365065e4de04a454a5c2ce21be335a23a01e4
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Tegra: memctrl_v2: get chip revision using platform identifiers ...

This patch switches to the functions which identify the underlying
platform in order to calculate the chip SKU.

Change-Id: I20cf5623465289ccfab28d6578efcf762bfeb456
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186: mce: read MCE's firmware version on "real" platforms ...

This patch runs the MCE firmware's version check only if the underlying
platform has the capability to the run the firmware. MCE firmware is not
running on simulation platforms, identified by v0.3 or v0.6, read from the
Tegra Chip ID value.

Change-Id: I3b1788b1ee2a0d4464017bb879ac5792cb7022b8
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186: use helper functions to get major/minor version ...

This patch uses helper functions to read the chips's major and minor
version values.

Change-Id: I5b2530a31af5ab3778a8aa63380def4e9f9ee6ec
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186: memmap all UART controllers ...

This patch adds all the UART controllers to the memory map.

Change-Id: I035e55ca7bff0a96115102f2295981f9e3a5da6b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186: implement plat_get_syscnt_freq2() ...

Commit f3d3b31 replaced
plat_get_syscnt_freq by plat_get_syscnt_freq2 on all the
upstream platforms. This patch modifies the Tegra186 code
which is not present usptream, yet.

Change-Id: Ieda6168050a7769680a3a94513637fed03463a2d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: smmu: disable TCU prefetch for all the 64 contexts ...

This patch disables TCU prefetch for all the contexts in order
to improve SMMU performance.

Change-Id: I82ca49a0e396d9f064f5c62a5f00c4b2101d8459
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186: handlers to get BL31 arguments from previous bootloader ...

This patch overrides the default handlers to get BL31 arguments from the
previous bootloader. The previous bootloader stores the pointer to the
arguments in PMC secure scratch register #53.

BL31 is the first component running on the CPU, as there isn't a previous
bootloader. We set the RESET_TO_BL31 flag to enable the path which assumes
that there are no input parameters passed by the previous bootloader.

Change-Id: Idacc1df292a70c9c1cb4d5c3a774bd796175d5e8
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186: delete 'Video Memory Carveout' handling ...

This patch removes duplicate code from the platform's SiP handler
routine for processing Video Memory Carveout region requests and
uses the common SiP handler instead.

Change-Id: Ib307de017fd88d5ed3c816288327cae750a67806
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: memctrl_v2: TZRAM aperture configuration settings ...

This patch enables the configuration settings for the TZRAM
aperture by programming the base/size of the aperture and
restricting access to it. We allow only the CPU to read/write
by programming the access configuration registers to 0.

Change-Id: Ie16ad29f4c5ec7aafa972b0a0230b4790ad5619e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186: modify the return type for `plat_get_syscnt_freq()` ...

Commit c073fda upstream changed the
return type for `plat_get_syscnt_freq()` from uint64_t to unsigned
long long.

This patch modifies the return type for the Tegra186 platform.

Change-Id: Ic9e5c364b90972265576e271582a4347e5eaa6eb
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186: Enable ECC and Parity Protection for A02p SKUs ...

This patch enables ECC and Parity Protection for Cortex-A57 CPUs during boot,
for Tegra186 A02p SKUs.

Change-Id: I8522a6cb61f5e4fa9e0471f558a0c3ee8078370e
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186: mce: Uncore Perfmon ARI Programming ...

Uncore perfmon appears to the CPU as a set of uncore perfmon registers
which can be read and written using the ARI interface. The MCE code
sequence handles reads and writes to these registers by manipulating
the underlying T186 uncore hardware.

To access an uncore perfmon register, CPU software writes the ARI
request registers to specify

* whether the operation is a read or a write,
* which uncore perfmon register to access,
* the uncore perfmon unit, group, and counter number (if necessary),
* the data to write (if the operation is a write).

It then initiates an ARI request to run the uncore perfmon sequence in
the MCE and reads the resulting value of the uncore perfmon register
and any status information from the ARI response registers.

The NS world's MCE driver issues MCE_CMD_UNCORE_PERFMON_REQ command
for the EL3 layer to start the entire sequence. Once the request
completes, the NS world would receive the command status in the X0
register and the command data in the X1 register.

Change-Id: I20bf2eca2385f7c8baa81e9445617ae711ecceea
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186: implement `get_target_pwr_state` handler ...

This patch implements the `get_target_pwr_state` handler for Tegra186
SoCs. The SoC port uses this handler to find out the cluster/system
state during CPU_SUSPEND, CPU_OFF and SYSTEM_SUSPEND calls.

The MCE firmware controls the power state of the CPU/CLuster/System,
so we query it to get the state and act accordingly.

Change-Id: I86633d8d79aec7dcb405d2301ac69910f93110fe
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra186: mce: add the mce_update_cstate_info() helper function ...

This patch adds a helper function to the MCE driver to allow its
clients to issue UPDATE_CSTATE_INFO requests, without having to
setup the CPU context struct.

We introduced a struct to encapsulate the request parameters, that
clients can pass on to the MCE driver. The MCE driver gets the
parameters from the struct and programs the hardware accordingly.

Change-Id: I02bce57506c4ccd90da82127805d6b564375cbf1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Merge pull request #875 from vwadekar/tegra186-platform-support-v2 ...

Tegra186 platform support v2

Enable all A53 and A57 errata workarounds for Juno ...

Juno platform Makefile is responsible for enabling all the relevant
errata. As the Juno platform port does not know which revision of Juno
the TF
is compiled for, the revision of the cores are unknown and so all errata
up to this date are needed on at least one revision of Juno.

Change-Id: I38e1d6efc17e703f2bd55e0714f8d8fa4778f696
Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>

Merge pull request #880 from Summer-ARM/sq/tcr-memory-attribution ...

Add support to change xlat_tables to non-cacheable

Upgrade mbed TLS version ...

This patch updates the User Guide to recommend the latest version
of mbed TLS library to use with ARM Trusted Firmware.

 - Upgrade mbed TLS library:   2.2.1 -> 2.4.2

Change-Id: Ifb5386fec0673d6dbfdaa474233e397afc279c85

Merge pull request #870 from douglas-raillard-arm/dr/remove_asm_signed_test ...

Replace ASM signed tests with unsigned

Merge pull request #879 from Summer-ARM/sq/mt-support ...

ARM platforms: Add support for MT bit in MPIDR

Merge pull request #878 from vwadekar/tegra-memctrlv2-coverity-fix ...

Tegra: memctrl_v2: fix logic to calculate TZRAM_ADDR_HI bits

Add support to change xlat_tables to non-cacheable ...

This patch adds an additional flag `XLAT_TABLE_NC` which marks the
translation tables as Non-cacheable for MMU accesses.

Change-Id: I7c28ab87f0ce67da237fadc3627beb6792860fd4
Signed-off-by: Summer Qin <summer.qin@arm.com>