Merge "allwinner: Move the NOBITS region to SRAM A1" into integration

Merge "intel: Remove un-needed checks for qspi driver r/w" into integration

Merge changes from topic "tegra-misra-21.1-fixes" into integration ...

* changes:
  Tegra194: drivers: fix violations of MISRA Rule 21.1
  Tegra: include: fix violations of MISRA Rule 21.1

Merge "docs: GCC toolchain upgrade to version 9.2-2019.12" into integration

intel: Remove un-needed checks for qspi driver r/w ...

This patch removes un-needed r/w parameter checks for qspi driver. The
driver can actually access any offset and size.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: If60b2c016aa91e2c24ddc57c6ad410c8dc5dcf53

Tegra194: drivers: fix violations of MISRA Rule 21.1 ...

This patch fixes the violations of Rule 21.1 from all the
header files.

Rule 21.1 "#define and #undef shall not be used on a reserved
           identifier or reserved macro name"

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I12e17a5d7158defd33b03416daab3049749905fc

Tegra: include: fix violations of MISRA Rule 21.1 ...

This patch fixes the violations of Rule 21.1 from all the
Tegra common header files.

Rule 21.1 "#define and #undef shall not be used on a reserved
           identifier or reserved macro name"

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I2e117645c110e04c13fa86ebbbb38df4951d2185

docs: GCC toolchain upgrade to version 9.2-2019.12 ...

This toolchain provides multiple cross compilers and are publicly
available on developer.arm.com

We build TF-A in CI using:
AArch32 bare-metal target (arm-none-eabi)
AArch64 ELF bare-metal target (aarch64-none-elf)

Change-Id: I910200174d5bad985504d1af4a1ae5819b524003
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

Merge "Unify type of "cpu_idx" across PSCI module." into integration

Unify type of "cpu_idx" across PSCI module. ...

NOTE for platform integrators:
   API `plat_psci_stat_get_residency()` third argument
   `last_cpu_idx` is changed from "signed int" to the
   "unsigned int" type.

Issue / Trouble points
1. cpu_idx is used as mix of `unsigned int` and `signed int` in code
with typecasting at some places leading to coverity issues.

2. Underlying platform API's return cpu_idx as `unsigned int`
and comparison is performed with platform specific defines
`PLAFORM_xxx` which is not consistent

Misra Rule 10.4:
The value of a complex expression of integer type may only be cast to
a type that is narrower and of the same signedness as the underlying
type of the expression.

Based on above points, cpu_idx is kept as `unsigned int` to match
the API's and low-level functions and platform defines are updated
where ever required

Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: Ib26fd16e420c35527204b126b9b91e8babcc3a5c

Merge "rcar_gen3: plat: Pass DT to OpTee OS" into integration

Merge "plat: nvidia: remove spurious UTF-8 characters at top of platform files" into integration

Merge "FVP: Remove re-definition of topology related build options" into integration

Merge "FVP: Stop reclaiming init code with Clang builds" into integration

Merge "rcar_gen3: drivers: ddr: Move DDR drivers out of staging" into integration

Merge "Revert "GCC: Upgrade to version 9.2-2019.12 of toolchain"" into integration

FVP: Remove re-definition of topology related build options ...

This patch removes re-definition of the following FVP build
options from plat\arm\board\fvp\fvp_def.h:
 'FVP_CLUSTER_COUNT'
 'FVP_MAX_CPUS_PER_CLUSTER'
 'FVP_MAX_PE_PER_CPU'
which are set in platform.mk.

This fixes a potential problem when a build option set in
platform.mk file can be re-defined in fvp_def.h header file
used by other build component with a different makefile which
does not set this option.
Ref. GENFW-3505.

Change-Id: I4288629920516acf2c239c7b733f92a0c5a812ff
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

Merge "smccc: add get smc function id num macro" into integration

Merge "Simplify PMF helper macro definitions across header files" into integration

Merge "Remove redundant declarations." into integration

Merge "Tegra194: mce: fix error code signedness" into integration

smccc: add get smc function id num macro ...

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I2953f0a6f35bc678402bc185640d1f328b065af5

plat: nvidia: remove spurious UTF-8 characters at top of platform files ...

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Iee7fb43990047b27972e99572ec4b3dc4e5c0423

Simplify PMF helper macro definitions across header files ...

In further patches, we aim to enable -Wredundant-decls by default.
This rearragement of helper macros is necessary to make Coverity
tool happy as well as making sure there are no redundant function
declarations for PMF related declarations.

Also, PMF related macros were added to provide appropriate function
declarations for helper APIs which capture PSCI statistics.

Change-Id: I36273032dde8fa079ef71235ed3a4629c5bfd981
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

Remove redundant declarations. ...

In further patches, we wish to enable -wredundant-decls check as
part of warning flags by default.

Change-Id: I43410d6dbf40361a503c16d94ccf0f4cf29615b7
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

Revert "GCC: Upgrade to version 9.2-2019.12 of toolchain" ...

This reverts commit de9bf1d.

Change-Id: Iebb6297ce290a10ee850bf6a9c71e7eb530b085f

Tegra194: mce: fix error code signedness ...

The MCE driver's helper functions were using postive values as error
codes.

This patch updates the functions to return negative values as error
codes instead. Some functions are updated to use the right error code.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I3e2ecc30a6272a357e1a22ec850543fde2a694f6

Merge "A5DS: Change boot address to point to DDR address" into integration

Merge "A5DS: Correct system freq, Cache Writeback Granule" into integration

FVP: Stop reclaiming init code with Clang builds ...

The reclaim init code functionality relies on forward reference in the
linker script. The LLVM linker does not process it correctly.

Change-Id: I993aeb9587bfa07af25b60ed823a6a2c5e970c94
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>