LuminaSensum/arm-trusted-firmware

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LuminaSensum / arm-trusted-firmware

2019-09-12	b90f207 Browse files » Invalidate dcache build option for bl2 entry at EL3 ... Some of the platform (ie. Agilex) make use of CCU IPs which will only be initialized during bl2_el3_early_platform_setup. Any operation to the cache beforehand will crash the platform. Hence, this will provide an option to skip the data cache invalidation upon bl2 entry at EL3 Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I2c924ed0589a72d0034714c31be8fe57237d1f06 Hadi Asyrafi authored on 20 Aug 2019 Soby Mathew committed on 12 Sep 2019
	2fc6ffc Browse files » Merge "libc: fix sparse warning for __assert()" into integration Soby Mathew authored on 12 Sep 2019 TrustedFirmware Code Review committed on 12 Sep 2019
	4210af0 Browse files » Merge "doc: Updated user guide with new Mbed TLS version number" into integration Soby Mathew authored on 12 Sep 2019 TrustedFirmware Code Review committed on 12 Sep 2019
	8911a32 Browse files » Merge "intel: agilex: Fix psci power domain off" into integration Soby Mathew authored on 12 Sep 2019 TrustedFirmware Code Review committed on 12 Sep 2019
	91624b7 Browse files » Merge changes from topic "jc/mte_enable" into integration ... * changes: Add documentation for CTX_INCLUDE_MTE_REGS Enable MTE support in both secure and non-secure worlds Soby Mathew authored on 12 Sep 2019 TrustedFirmware Code Review committed on 12 Sep 2019
	5beeec7 Browse files » Merge "plat: xilinx: zynqmp: Initialize IPI table from zynqmp_config_setup()" into integration Soby Mathew authored on 12 Sep 2019 TrustedFirmware Code Review committed on 12 Sep 2019
	18eb002 Browse files » Merge "Zeus: apply the MSR SSBS instruction" into integration Soby Mathew authored on 12 Sep 2019 TrustedFirmware Code Review committed on 12 Sep 2019
	684b3a0 Browse files » Merge "Add UBSAN support and handlers" into integration Soby Mathew authored on 12 Sep 2019 TrustedFirmware Code Review committed on 12 Sep 2019
	f38e518 Browse files » Merge changes I072c0f61,I798401f4,I9648ef55,I7225d9fa,Ife682288, ... into integration ... * changes: rcar_gen3: drivers: ddr_b: Update DDR setting for H3, M3, M3N rcar_gen3: drivers: qos: update QoS setting rcar_gen3: drivers: ddr_b: Fix checkpatch errors in headers rcar_gen3: drivers: ddr_b: Fix line-over-80s rcar_gen3: drivers: ddr_b: Further checkpatch cleanups rcar_gen3: drivers: ddr_b: Clean up camel case rcar_get3: drivers: ddr_b: Basic checkpatch fixes rcar_get3: drivers: ddr: Partly unify register macros between DDR A and B rcar_get3: drivers: ddr: Clean up common code Soby Mathew authored on 12 Sep 2019 TrustedFirmware Code Review committed on 12 Sep 2019
	9af73b3 Browse files » Merge changes from topic "amlogic-refactoring" into integration ... * changes: amlogic: Fix includes order amlogic: Fix header guards amlogic: Fix prefixes in the SoC specific files amlogic: Fix prefixes in the PM code amlogic: Fix prefixes in the SCPI related code amlogic: Fix prefixes in the MHU code amlogic: Fix prefixes in the SIP/SVC code amlogic: Fix prefixes in the thermal driver amlogic: Fix prefixes in the private header file amlogic: Fix prefixes in the efuse driver amlogic: Fix prefixes in the platform macros file amlogic: Fix prefixes in the helpers file amlogic: Rework Makefiles amlogic: Move the SIP SVC code to common directory amlogic: Move topology file to common directory amlogic: Move thermal code to common directory amlogic: Move MHU code to common directory amlogic: Move efuse code to common directory amlogic: Move platform macros assembly file to common directory amlogic: Introduce unified private header file amlogic: Move SCPI code to common directory amlogic: Move the SHA256 DMA driver to common directory amlogic: Move assembly helpers to common directory amlogic: Introduce directory parameters in the makefiles meson: Rename platform directory to amlogic Soby Mathew authored on 12 Sep 2019 TrustedFirmware Code Review committed on 12 Sep 2019
	afac968 Browse files » intel: agilex: Fix psci power domain off ... Disable gic cpu interface for powered down cpu. This patch also removes core reset during power off as core reset will be done during power on Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I2ca96d876b6e71e56d24a9a7e184b6d6226b8673 Hadi Asyrafi committed on 12 Sep 2019
2019-09-11	b562187 Browse files » amlogic: Fix includes order ... As part of the code refactoring fix the order of the include files across all the source files. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Ice72f687cc26ee881a9051168149467688100cfb Carlo Caione committed on 11 Sep 2019
	421b67b Browse files » amlogic: Fix header guards ... Make the header guards more generic and contextually remove the GXBB_BL31_PLAT_PARAM_VAL value that is unused on the GXL platform. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: I842fa2e084e71280ae17b39c67877e844821a171 Carlo Caione committed on 11 Sep 2019
	749b334 Browse files » Merge "mbedtls: use #include <...> instead of "..."" into integration Soby Mathew authored on 11 Sep 2019 TrustedFirmware Code Review committed on 11 Sep 2019
	cd3c5b4 Browse files » Modify FVP makefile for cores that support both AArch64/32 ... Some cores support only AArch64 from EL1 and above, e.g. A76, N1 etc. If TF-A is compiled with CTX_INCLUDE_AARCH32_REGS=0 so as to properly handle those cores, only the AArch64 cores' assembly is included in the TF-A binary. In other words, for FVP, TF-A assumes that AArch64 only cores will never exist in the same cluster with cores that also support AArch32. However, A55 and A75 can be used as AArch64 only cores, despite supporting AArch32, too. This patch enables A55 and A75 to exist in clusters together with AArch64 cores. Change-Id: I58750ad6c3d76ce77eb354784c2a42f2c179031d Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> John Tsichritzis committed on 11 Sep 2019
	07f979b Browse files » Zeus: apply the MSR SSBS instruction ... Zeus supports the SSBS mechanism and also the new MSR instruction to immediately apply the mitigation. Hence, the new instruction is utilised in the Zeus-specific reset function. Change-Id: I962747c28afe85a15207a0eba4146f9a115b27e7 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com> John Tsichritzis committed on 11 Sep 2019
	1f46197 Browse files » Add UBSAN support and handlers ... This patch adds support for the Undefined Behaviour sanitizer. There are two types of support offered - minimalistic trapping support which essentially immediately crashes on undefined behaviour and full support with full debug messages. The full support relies on ubsan.c which has been adapted from code used by OPTEE. Change-Id: I417c810f4fc43dcb56db6a6a555bfd0b38440727 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com> Justin Chadwell committed on 11 Sep 2019
2019-09-10	f906a44 Browse files » libc: fix sparse warning for __assert() ... Sparse warns this: lib/libc/assert.c:29:6: error: symbol '__assert' redeclared with different type (originally declared at include/lib/libc/assert.h:36) - different modifiers Add __dead2 to match the header declaration and C definition. I also changed '__dead2 void' to 'void __dead2' for the consistency with other parts. Change-Id: Iefa4f0e787c24fa7e7e499d2e7baf54d4deb49ef Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Masahiro Yamada committed on 10 Sep 2019
	705bed5 Browse files » plat: xilinx: zynqmp: Initialize IPI table from zynqmp_config_setup() ... Common ipi_table needs to be initialized before using any IPI command (i.e send/receive). Move zynqmp ipi config table initialization from sip_svc_setup() to zynqmp_config_setup(). Change-Id: Ic8aaa0728a43936cd4c6e1ed590e01ba8f0fbf5b Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> Jolly Shah committed on 10 Sep 2019
	ebf851e Browse files » stm32mp1: manage CONSOLE_FLAG_TRANSLATE_CRLF and cleanup driver ... The STM32 console driver was pre-pending '\r' before '\n'. It is now managed by the framework with the flag: CONSOLE_FLAG_TRANSLATE_CRLF. Remove the code in driver, and add the flag for STM32MP1. Change-Id: I5d0d5d5c4abee0b7dc11c2f8707b1b5cf10149ab Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier committed on 10 Sep 2019
	0289ab9 Browse files » Merge changes from topic "yg/stm32mp1_wdg_updates" into integration ... * changes: mmc: stm32_sdmmc2: correctly manage block size mmc: stm32_sdmmc2: manage max-frequency property from DT stm32mp1: move check_header() to common code stm32mp1: keep console during runtime stm32mp1: sp_min: initialize MMU and cache earlier stm32mp1: add support for LpDDR3 stm32mp1: use a common function to check spinlock is available clk: stm32mp: enable RTCAPB clock for dual-core chips stm32mp1: check if the SoC is single core stm32mp1: print information about board stm32mp1: print information about SoC stm32mp1: add watchdog support Soby Mathew authored on 10 Sep 2019 TrustedFirmware Code Review committed on 10 Sep 2019
	40b0651 Browse files » Add python configuration for editorconfig ... As it currently is, python files are formatted using the general rules in .editorconfig - this means that 8-character hard tabs are used, which is not the recommended behaviour according to the PEP-8 standard. This patch correct this, and additionally limits the line length to 79 characters as required by the standard. Change-Id: I3b5c0aff12034c4184d4555aab36490cdb3885da Signed-off-by: Justin Chadwell <justin.chadwell@arm.com> Justin Chadwell committed on 10 Sep 2019
2019-09-09	0d8cb49 Browse files » mediatek: mt8183: Support coreboot configuration ... When built for coreboot, we want to enable coreboot library to have better integration. For example, serial console should be initialized by coreboot_serial instead of hard-coded values. Most coreboot configuration will enable memory console, which needs larger XLAT_TABLES so MAX_XLAT_TABLES is increased; and to support that, TZRAM_SIZE also need to be enlarged. Change-Id: I08cf22df2fa26e48284e323d22ad8ce73a6ea803 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Hung-Te Lin authored on 2 May 2019 kenny liang committed on 9 Sep 2019
	3d91c9c Browse files » mediatek: mt8183: support system reset ... Implement system reset handler. Change-Id: I535ee414616dde8d2b59dec5a723a540a3a1341d Signed-off-by: kenny liang <kenny.liang@mediatek.com> kenny liang committed on 9 Sep 2019
	a561205 Browse files » mediatek: mt8183: pass platform parameters ... Add plat parameter structs to support BL2 to pass variable-length, variable-type parameters to BL31. The parameters are structured as a link list. During BL31 setup time, we traverse the list to process each parameter. Signed-off-by: kenny liang <kenny.liang@mediatek.com> Change-Id: Ie84cfc9606656fb1d2780a68cadf27e09afa6628 kenny liang committed on 9 Sep 2019
	50cd952 Browse files » mediatek: mt8183: add GPIO driver ... Add GPIO driver. Change-Id: I8c35ce4ea247f3726081b0bbb95f0930c2b82517 Signed-off-by: kenny liang <kenny.liang@mediatek.com> kenny liang committed on 9 Sep 2019
	e977b4d Browse files » mediatek: mt8183: support system off ... - Add PMIC driver - Add RTC drvier - Refactor PMIC and RTC to mediatek/common - Implement system off handler Change-Id: If76497646ace1b78bc9a5fa0110b652fe512281a Signed-off-by: kenny liang <kenny.liang@mediatek.com> kenny liang committed on 9 Sep 2019
	7352f32 Browse files » mediatek: mt8183: support CPU hotplug ... - Add DCM driver - Add SPMC driver - Implement core and cluster power on/off handlers Change-Id: I902002f8ea6f98fd73bf259188162b10d3939c72 Signed-off-by: kenny liang <kenny.liang@mediatek.com> kenny liang committed on 9 Sep 2019
	f992b96 Browse files » mediatek: mt8183: refine GIC driver ... Refine MTK GIC driver. Remove unused codes. Signed-off-by: kenny liang <kenny.liang@mediatek.com> Change-Id: I39e05ce7aa3c257e237fbc8e661cdde65cbcec7c kenny liang committed on 9 Sep 2019
	0c411c7 Browse files » Assert if power level value greater then PSCI_INVALID_PWR_LVL ... Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I4a496d5a8e7a9a127cd6224c968539eb74932fca Deepika Bhavnani committed on 9 Sep 2019