LuminaSensum/arm-trusted-firmware

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LuminaSensum / arm-trusted-firmware

2020-10-28	fc86063 Browse files » Merge "aarch64/arm: Add compiler barrier to barrier instructions" into integration André Przywara authored on 28 Oct 2020 TrustedFirmware Code Review committed on 28 Oct 2020
	6e97b22 Browse files » Merge changes from topic "mbox-patches" into integration ... * changes: intel: common: Clean up mailbox and sip header intel: clear 'PLAT_SEC_ENTRY' in early platform setup Manish Pandey authored on 28 Oct 2020 TrustedFirmware Code Review committed on 28 Oct 2020
	350c04f Browse files » Merge changes I07448d85,If85be70b,Ie6802d6d,I67a9abef into integration ... * changes: mediatek: mt8192: add timer support mediatek: mt8192: Add reboot function for PSCI mediatek: mt8192: add sys_cirq driver mediatek: mt8192: add GPIO driver support Manish Pandey authored on 28 Oct 2020 TrustedFirmware Code Review committed on 28 Oct 2020
	4a12801 Browse files » mediatek: mt8192: add timer support ... add timer driver. Signed-off-by: Dehui Sun <dehui.sun@mediatek.com> Change-Id: I07448d85a15bb14577b05e4f302860d609420ba7 Dehui Sun authored on 2 Jul 2020 Nina Wu committed on 28 Oct 2020
	0f40824 Browse files » mediatek: mt8192: Add reboot function for PSCI ... Add system_reset function in psci ops Change-Id: If85be70b8ae9d6487e02626356f0ff1e78b76de9 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Nina Wu committed on 28 Oct 2020
	b6cec33 Browse files » mediatek: mt8192: add sys_cirq driver ... 1.add sys_cirq driver 2.add gic api for cirq Change-Id: Ie6802d6ddcf7dde3412a050736dfdc85f97cb51b Signed-off-by: gtk_pangao <gtk_pangao@mediatek.com> gtk_pangao authored on 19 Dec 2019 Nina Wu committed on 28 Oct 2020
2020-10-27	2be491b Browse files » aarch64/arm: Add compiler barrier to barrier instructions ... When issuing barrier instructions like DSB or DMB, we must make sure that the compiler does not undermine out efforts to fence off instructions. Currently the compiler is free to move the barrier instruction around, in respect to former or later memory access statements, which is not what we want. Add a compiler barrier to the inline assembly statement in our DEFINE_SYSOP_TYPE_FUNC macro, to make sure memory accesses are not reordered by the compiler. This is in line with Linux' definition: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/include/asm/barrier.h Since those instructions share a definition, apart from DSB and DMB this now also covers some TLBI instructions. Having a compiler barrier there also is useful, although we probably have stronger barriers in place already. Change-Id: If6fe97b13a562643a643efc507cb4aad29daa5b6 Reported-by: Alexandru Elisei <alexandru.elisei@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Andre Przywara committed on 27 Oct 2020
2020-10-27	c036570 Browse files » Merge "plat: marvell: armada: Fix dependences for target fip" into integration Manish Pandey authored on 27 Oct 2020 TrustedFirmware Code Review committed on 27 Oct 2020
2020-10-26	00ad74c Browse files » Merge "SPMC: adjust device region for first secure partition" into integration Olivier Deprez authored on 26 Oct 2020 TrustedFirmware Code Review committed on 26 Oct 2020
2020-10-26	054af8f Browse files » mediatek: mt8192: add GPIO driver support ... add GPIO driver Change-Id: I67a9abef078e7a62b34dfbd366b45c03892800cd Signed-off-by: Po Xu <jg_poxu@mediatek.com> Po Xu committed on 26 Oct 2020
2020-10-23	516f322 Browse files » intel: common: Clean up mailbox and sip header ... Sort and rearrange definitions in both mailbox and sip header to increase readability and maintainability. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I5544c2f17efdf3174757c55afd8cc1062fbae856 Abdul Halim, Muhammad Hadi Asyrafi committed on 23 Oct 2020
	7f56f24 Browse files » intel: clear 'PLAT_SEC_ENTRY' in early platform setup ... Ensure 'PLAT_SEC_ENTRY' is cleared during early platform setup. This is to prevent the slave CPU cores jump to the stale entry point after warm reset when using U-Boot SPL as first stage boot loader. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Change-Id: I3294ce2f74aa691d0cf311fa30f27f9d4fb8800a Chee Hong Ang authored on 24 Apr 2020 Abdul Halim, Muhammad Hadi Asyrafi committed on 23 Oct 2020
	95fca11 Browse files » Merge "docs: marvell: update ddr3 build instructions" into integration Varun Wadekar authored on 23 Oct 2020 TrustedFirmware Code Review committed on 23 Oct 2020
	9c28689 Browse files » Merge changes I5ae9d08b,I5cbbd7eb,Idb389223 into integration ... * changes: plat: marvell: armada: Building ${DOIMAGETOOL} is only for a8k plat: marvell: armada: Fix including plat/marvell/marvell.mk file plat: marvell: armada: a3k: When WTP is empty do not define variables and targets which depends on it Varun Wadekar authored on 23 Oct 2020 TrustedFirmware Code Review committed on 23 Oct 2020
2020-10-22	083dbb6 Browse files » Merge "plat/qemu_sbsa: Remove cortex_a53 and aem_generic" into integration Manish Pandey authored on 22 Oct 2020 TrustedFirmware Code Review committed on 22 Oct 2020
2020-10-21	d0d63af Browse files » SPMC: adjust device region for first secure partition ... For the first partition, mark first 2GB as device memory excluding the Trusted DRAM region reserved for the SPMC. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I3ff110b3facf5b6d41ac2519ff6ca5e30a0a502b Olivier Deprez committed on 21 Oct 2020
	bc98a2e Browse files » Merge changes from topic "tc0_sel2_spmc" into integration ... * changes: plat: tc0: Configure TZC with secure world regions plat: tc0: Enable SPMC execution at S-EL2 plat: tc0: Add TZC DRAM1 region for SPMC and trusted OS plat: arm: Make BL32_BASE platform dependent when SPD_spmd is enabled plat: tc0: Disable SPE Manish Pandey authored on 21 Oct 2020 TrustedFirmware Code Review committed on 21 Oct 2020
	c4d919e Browse files » Merge changes from topic "tc0_sel2_spmc" into integration ... * changes: lib: el3_runtime: Fix SPE system registers in el2_sysregs_context lib: el3_runtime: Conditionally save/restore EL2 NEVE registers lib: el3_runtime: Fix aarch32 system registers in el2_sysregs_context Manish Pandey authored on 21 Oct 2020 TrustedFirmware Code Review committed on 21 Oct 2020
	d1ff30d Browse files » plat/qemu_sbsa: Remove cortex_a53 and aem_generic ... The qemu_sbsa platform uses 42bit address size but the cortex-a53 only supports 40bit addressing, the cpu is incompatible with the platform. The aem_generic is also not used with qemu_sbsa, in fact, the platform currently only properly supports the cortex-a57 cpu. Change-Id: I91c92533116f1c3451d01ca99824e91d3d58df14 Signed-off-by: Tomas Pilar <tomas@nuviateam.com> Tomas Pilar committed on 21 Oct 2020
	b5e3d54 Browse files » plat: marvell: armada: Building ${DOIMAGETOOL} is only for a8k ... Currently a3k target is misusing ${DOIMAGETOOL} target for building flash and UART images. It is not used for building image tool. So move ${DOIMAGETOOL} target from common marvell include file into a8k include file and add correct invocation of ${MAKE} into a3k for building flash and UART images. Part of this change is also checks that MV_DDR_PATH for a3k was specified by user as this option is required for building a3k flash and UART images. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I5ae9d08b8505460933f17836c9b6435fd6e51bb6 Pali Rohár committed on 21 Oct 2020
2020-10-20	bd260fc Browse files » Merge "docs: code review guidelines" into integration Manish Pandey authored on 20 Oct 2020 TrustedFirmware Code Review committed on 20 Oct 2020
	879b5b8 Browse files » plat: tc0: Configure TZC with secure world regions ... This includes configuration for SPMC and trusted OS. Change-Id: Ie24df200f446b3f5b23f5f764b115c7191e6ada3 Signed-off-by: Usama Arif <usama.arif@arm.com> Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Usama Arif authored on 26 Aug 2020 Manish Pandey committed on 20 Oct 2020
	b0d1275 Browse files » plat: tc0: Enable SPMC execution at S-EL2 ... This patch enables SPMC execution at S-EL2 by adding below changes - Map TC0_MAP_TZC_DRAM1 for loading SPMC - Add details of cactus test secure partitions - Adds tc0 spmc manifest file with details on secure partitions - Inlcude TOS_FW_CONFIG when SPM is spmd - Increases bl2 image size SPMC at S-EL2 is only enabled when build with SPD=spmd. Change-Id: I4c5f70911903c232ee8ecca57f1e288d6b1cd647 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Arunachalam Ganapathy authored on 22 Sep 2020 Manish Pandey committed on 20 Oct 2020
	a3ecbb3 Browse files » plat: tc0: Add TZC DRAM1 region for SPMC and trusted OS ... - Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for TC0_TZC_DRAM1 - Add TC0_NS_DRAM1 base and mapping - Reserve memory region in tc0.dts Change-Id: If2431f7f68e4255e28c86a0e89637dab7c424a13 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Arunachalam Ganapathy authored on 22 Sep 2020 Manish Pandey committed on 20 Oct 2020
	d32113c Browse files » plat: arm: Make BL32_BASE platform dependent when SPD_spmd is enabled ... To support platforms without Trusted DRAM this patch defines PLAT_ARM_SPMC_BASE and enables platform to use either Trusted DRAM or DRAM region behind TZC. Change-Id: Icaa5c7d33334258ff27e8e0bfd0812c304e68ae4 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Arunachalam Ganapathy authored on 27 Jul 2020 Manish Pandey committed on 20 Oct 2020
	c398caf Browse files » plat: tc0: Disable SPE ... Statistical Profiling Extension is not supported by Matterhorn core Change-Id: Iec652f1c6d6b6a9bf118ba682276a7c70a6abc0d Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Arunachalam Ganapathy authored on 28 May 2020 Manish Pandey committed on 20 Oct 2020
	2b036b7 Browse files » lib: el3_runtime: Fix SPE system registers in el2_sysregs_context ... Include EL2 registers related to SPE in EL2 context save/restore routines if architecture supports it and platform wants to use these features in Secure world. Change-Id: Ie01a2c38fa5f6c907276eddec120fdfb222561a6 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Arunachalam Ganapathy authored on 9 Oct 2020 Manish Pandey committed on 20 Oct 2020
	062f8aa Browse files » lib: el3_runtime: Conditionally save/restore EL2 NEVE registers ... Include EL2 registers related to Nested Virtualization in EL2 context save/restore routines if architecture supports it and platform wants to use these features in Secure world. Change-Id: If006ab83bbc2576488686f5ffdff88b91adced5c Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Arunachalam Ganapathy authored on 28 May 2020 Manish Pandey committed on 20 Oct 2020
	0f777ea Browse files » lib: el3_runtime: Fix aarch32 system registers in el2_sysregs_context ... AArch64-only platforms do not implement AArch32 at EL1 and higher ELs. In such cases the build option CTX_INCLUDE_AARCH32_REGS is set to 0. So don't save/restore aarch32 system registers in el2_sysregs_context save/restore routines if CTX_INCLUDE_AARCH32_REGS is set to 0. Change-Id: I229cdd46136c4b4bc9623b02eb444d904e09ce5a Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Arunachalam Ganapathy authored on 26 May 2020 Manish Pandey committed on 20 Oct 2020
2020-10-19	0412b73 Browse files » plat: marvell: armada: Fix including plat/marvell/marvell.mk file ... Include file plat/marvell/marvell.mk for platform A3700 was included two times. Once from file plat/marvell/armada/a3k/common/a3700_common.mk and second time from common file plat/marvell/armada/common/marvell_common.mk. It caused following warning every time was make called: plat/marvell/marvell.mk:51: warning: overriding recipe for target 'mrvl_clean' plat/marvell/marvell.mk:51: warning: ignoring old recipe for target 'mrvl_clean' Change in this commit removes inclusion of plat/marvell/marvell.mk file in common file plat/marvell/armada/common/marvell_common.mk. As a80x0 platform needs this include file, add it also into a80x0 platform specific include file lat/marvell/armada/a8k/common/a8k_common.mk. Also moves inclusion of plat/marvell/marvell.mk file in a3700 platform file plat/marvell/armada/a3k/common/a3700_common.mk at correct place. Global plat/marvell/marvell.mk expects that variables DOIMAGEPATH and DOIMAGETOOL are already defined, but it defines MARVELL_SECURE_BOOT variable which is needed by plat/marvell/armada/a3k/common/a3700_common.mk. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I5cbbd7eb8a3376924419f9850516b2a4924be5aa Pali Rohár committed on 19 Oct 2020