stm32mp1: SCMI clock and reset service in SP_MIN ...

This change implements platform services for stm32mp1 to expose clock
and reset controllers over SCMI clock and reset domain protocols
in sp_min firmware.

Requests execution use a fastcall SMC context using a SiP function ID.
The setup allows the create SCMI channels by assigning a specific
SiP SMC function ID for each channel/agent identifier defined. In this
change, stm32mp1 exposes a single channel and hence expects single
agent at a time.

The input payload in copied in secure memory before the message
in passed through the SCMI server drivers. BL32/sp_min is invoked
for a single SCMI message processing and always returns with a
synchronous response message passed back to the caller agent.

This change fixes and updates STM32_COMMON_SIP_NUM_CALLS that was
previously wrongly set 4 whereas only 1 SiP SMC function ID was to
be counted. STM32_COMMON_SIP_NUM_CALLS is now set to 3 since the
2 added SiP SMC function IDs for SCMI services.

Change-Id: Icb428775856b9aec00538172aea4cf11e609b033
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

dts: bindings: stm32mp1: define SCMI clock and reset domain IDs ...

Define the platform SCMI clocks and reset domains for stm32mp1 family.
SCMI agent 0 accesses clock/reset controllers under RCC TZEN hardening.
SCMI agent 1 accesses clock controllers under RCC MCKPROT hardening.

Change-Id: I52e906f846d445a3e6850e5f2e1584da14692553
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

Merge "drivers/stm32_hash: register resources as secure or not" into integration

Merge "drivers/stm32_gpio: register GPIO resources as secure or not" into integration

Merge "drivers/stm32_iwdg: register IWDG resources as secure or not" into integration

Merge "drivers/stm32mp_pmic: register PMIC resources as secure or not" into integration

Merge "stm32mp1: register shared resource per GPIO bank/pin" into integration

Merge "stm32mp1: register shared resource per IOMEM address" into integration

Merge "stm32mp1: allow non-secure access to reset upon periph registration" into integration

Merge "stm32mp1: allow non-secure access to clocks upon periph registration" into integration

Merge "stm32mp1: shared resources: peripheral registering" into integration

Merge "drivers: st: clock: register parent of secure clocks" into integration

Merge "stm32mp1: shared resources: add trace messages" into integration

Merge "fiptool: return zero status on help and help <command>" into integration

Merge changes from topic "fpga_cmdline" into integration ...

* changes:
  arm_fpga: Predefine DTB and BL33 load addresses
  arm_fpga: Add Klein and Matterhorn support
  arm_fpga: Support more CPU clusters

Merge "io_storage: remove redundant assigments" into integration

Merge "SPMD: fix boundary check if manifest is page aligned" into integration

SPMD: fix boundary check if manifest is page aligned ...

while mapping SPMC manifest page in the SPMD translation regime the
mapped size was resolved to zero if SPMC manifest base address is PAGE
aligned, causing SPMD to abort.

To fix the problem change mapped size to PAGE_SIZE if manifest base is
PAGE aligned.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I06cd39dbefaf492682d9bbb0c82b950dd31fb416

Merge "Add myself and Andre Przywara as code owners for the Arm FPGA platform port" into integration

Merge "plat/arm: Fix build failure due to increase in BL2 size" into integration

Merge changes I9feae1fc,I5cbe7192,I1867ece3,I85c2434a,If8edeeec, ... into integration ...

* changes:
  plat: marvell: armada: mcbin: squash several IO windows into one
  plat: marvell: armada: fix BL32 extra parameters usage
  drivers: marvell: Fix the LLC SRAM driver
  plat: marvell: armada: a8k: change CCU LLC SRAM mapping
  plat: marvell: armada: adjust trusted DRAM size to match OP-TEE OS
  drivers: marvell: mg_conf_cm3: pass comphy lane number to AP FW
  plat: marvell: armada: move mg conf related code to appropriate driver
  marvell: comphy: start AP FW when comphy AP mode selected
  drivers: marvell: mg_conf_cm3: add basic driver
  tools: doimage: change the binary image alignment to 16
  tools: doimage: migrate to mbedtls v2.8 APIs

Add myself and Andre Przywara as code owners for the Arm FPGA platform port ...

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I6d3949a971fada5a086b788dbe274f8451fcfc0d

plat/arm: Fix build failure due to increase in BL2 size ...

BL2 size gets increased due to the libfdt library update and 
that eventually cause no-optimization build failure for BL2 as below:
aarch64-none-elf-ld.bfd: BL2 image has exceeded its limit.
aarch64-none-elf-ld.bfd: region `RAM' overflowed by 4096 bytes
Makefile:1070: recipe for target 'build/fvp/debug/bl2/bl2.elf' failed
make: *** [build/fvp/debug/bl2/bl2.elf] Error 1

Fixed build failure by increasing BL2 image size limit by 4Kb.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I92a57eb4db601561a98e254b64994bb921a88db3

plat: marvell: armada: mcbin: squash several IO windows into one ...

There is no need to open tree different IO window when there is
possibility of having one covering required range.

Change-Id: I9feae1fc583df1f7d97d28161cf7601f43513856
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

plat: marvell: armada: fix BL32 extra parameters usage ...

Update missing code releated to the BL32 payload.

Change-Id: I5cbe71921467c53c45be5510f950cefdacc110e1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

drivers: marvell: Fix the LLC SRAM driver ...

- Fix the line address macro
- LLC invalidate and enable before ways lock for allocation
- Add support for limited SRAM size allocation
- Add SRAM RW test function

Change-Id: I1867ece3047566ddd7931bd7472e1f47fb42c8d4
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

plat: marvell: armada: a8k: change CCU LLC SRAM mapping ...

The LLC SRAM will be enabled in OP-TEE OS for usage as secure storage.
The CCU have to prepare SRAM window, but point to the DRAM-0 target
until the SRAM is actually enabled.
This patch changes CCU SRAM window target to DRAM-0
Remove dependence between LLC_SRAM and LLC_ENABLE and update the
build documentation.
The SRAМ base moved to follow the OP-TEE SHMEM area (0x05400000)

Change-Id: I85c2434a3d515ec37da5ae8eb729e3280f91c456
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

plat: marvell: armada: adjust trusted DRAM size to match OP-TEE OS ...

Area used as trusted DRAM is 12MB in Marvell OP-TEE OS module.
It is followed by 4MB of shared memory.

Change-Id: If8edeeec5861b529408baca25f78c06a0a440d8c
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

drivers: marvell: mg_conf_cm3: pass comphy lane number to AP FW ...

Since the AP process can be enabled on different setups, the information
about used comphy lane should be passed to AP FW. For instance:
- A8K development board uses comphy lane 2 for eth 0
- cn913x development board uses comphy lane 4 for eth 0

Change-Id: Icf001fb3eea4d9c24c09384e49844ecaf8655ad2
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

plat: marvell: armada: move mg conf related code to appropriate driver ...

Now when mg_conf_cm3 driver is present - move all relevant code there.

Change-Id: I444d9e877c450d6ee69ca3a49b547e4c3aeac0be
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>