plat/arm: Use common build flag for using generic sp804 driver ...

SP804 TIMER is not platform specific, and current code base adds
multiple defines to use this driver. Like FVP_USE_SP804_TIMER and
FVP_VE_USE_SP804_TIMER.

This patch removes platform specific build flag and adds generic
flag `USE_SP804_TIMER` to be set to 1 by platform if needed.

Change-Id: I5ab792c189885fd1b98ddd187f3a38ebdd0baba2
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

Merge changes from topic "sp_dual_signing" into integration ...

* changes:
  dualroot: add chain of trust for Platform owned SPs
  cert_create: add Platform owned secure partitions support

Merge "Use true instead of 1 in while" into integration

Merge changes from topic "bl1-misra" into integration ...

* changes:
  Specify signed-ness of constants
  Prevent colliding identifiers

Use true instead of 1 in while ...

This resolves MISRA defects such as:

    plat/common/plat_bl1_common.c:63:[MISRA C-2012 Rule 14.4 (required)]
    The condition expression "1" does not have an essentially boolean type.

Change-Id: I679411980ad661191fbc834a44a5eca5494fd0e2
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

Specify signed-ness of constants ...

We relyed on the default signed-ness of constants, which is usually
signed. This can create MISRA violations, such as:

     bl1/bl1_main.c:257:[MISRA C-2012 10.8 (required)] Cast of composite
     expression off essential type signed to essential type unsigned

These constants were only used as unsigned, so this patch makes them
explicitly unsigned.

Change-Id: I5f1310c881e936077035fbb1d5ffb449b45de3ad
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

Prevent colliding identifiers ...

There was a collision between the name of the typedef in the CASSERT and
something else, so we make the name of the typedef unique to the
invocation of DEFFINE_SVC_UUID2 by appending the name that's passed into
the macro. This eliminates the following MISRA violation:

    bl1/bl1_main.c:233:[MISRA C-2012 Rule 5.6 (required)] Identifier
    "invalid_svc_uuid" is already used to represent a typedef.

This also resolves MISRA rule 5.9.

These renamings are as follows:
  * tzram -> secram. This matches the function call name as it has
  sec_mem in it's  name
  * fw_config_base -> config_base. This file does not mess with
  hw_conig, so there's little chance of confusion

Change-Id: I8734ba0956140c8e29b89d0596d10d61a6ef351e
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

Merge "lib: cpus: denver: mark exception vectors as private" into integration

Merge "qti: Add RNG driver" into integration

qti: Add RNG driver ...

This patch adds RNG driver and use it to generate random number for stack
protection.

Change-Id: I73d79e68d08b5aa902dc7fad48e17a03f996178d
Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>

Merge "TF-A AMU: remove AMU enable info print" into integration

TF-A AMU: remove AMU enable info print ...

Following f3ccf036ecb1ae1628 the INFO print in amu_enable is causing
a lot of print outs on UART1 in DEBUG mode especially on PSCI test
cases because CPU_ON or SUSPEND operations call:
cm_prepare_el3_exit => enable_extensions_nonsecure => amu_enable.
PSCI SUSPEND is also very frequent in linux boot cases causing test
timeout failures.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I63581f8fa489d44b3b1d10af3b7f6fdf3af44720

dualroot: add chain of trust for Platform owned SPs ...

For dualroot CoT there are two sets of SP certificates, one owned by
Silicon Provider(SiP) and other owned by Platform. Each certificate can
have a maximum of 4 SPs.

This patch reduces the number of SiP owned SPs from 8 to 4 and adds
the remaining 4 to Plat owned SP.
Plat owned SP certificate is signed using Platform RoT key and
protected against anti-rollback using the Non-trusted Non-volatile
counter.

Change-Id: Idc3ddd87d6d85a5506a7435f45a6ec17c4c50425
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

cert_create: add Platform owned secure partitions support ...

Add support to generate a certificate named "plat-sp-cert" for Secure
Partitions(SP) owned by Platform.
Earlier a single certificate file "sip-sp-cert" was generated which
contained hash of all 8 SPs, with this change SPs are divided into
two categories viz "SiP owned" and "Plat owned" containing 4 SPs each.

Platform RoT key pair is used for signing.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I5bd493cfce4cf3fc14b87c8ed1045f633d0c92b6

Merge "TF-A AMU extension: fix detection of group 1 counters." into integration

Merge "plat/arm: Reduce size of BL31 binary" into integration

Merge changes from topic "release/14.0" into integration ...

* changes:
  docs: marvell: update PHY porting layer description
  docs: marvell: update path in marvell documentation
  docs: marvell: update build instructions with CN913x
  plat: marvell: octeontx: add support for t9130
  plat: marvell: t9130: add SVC support
  plat: marvell: t9130: update AVS settings
  plat: marvell: t9130: pass actual CP count for load_image
  plat: marvell: armada: a7k: add support to SVC validation mode
  plat: marvell: armada: add support for twin-die combined memory device

Merge "sc7180 platform support" into integration

TF-A AMU extension: fix detection of group 1 counters. ...

This patch fixes the bug when AMUv1 group1 counters was
always assumed being implemented without checking for its
presence which was causing exception otherwise.
The AMU extension code was also modified as listed below:
- Added detection of AMUv1 for ARMv8.6
- 'PLAT_AMU_GROUP1_NR_COUNTERS' build option is removed and
number of group1 counters 'AMU_GROUP1_NR_COUNTERS' is now
calculated based on 'AMU_GROUP1_COUNTERS_MASK' value
- Added bit fields definitions and access functions for
AMCFGR_EL0/AMCFGR and AMCGCR_EL0/AMCGCR registers
- Unification of amu.c Aarch64 and Aarch32 source files
- Bug fixes and TF-A coding style compliant changes.

Change-Id: I14e407be62c3026ebc674ec7045e240ccb71e1fb
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

plat/arm: Reduce size of BL31 binary ...

BL31 binary size is aligned to 4KB because of the
code in include\plat\arm\common\arm_reclaim_init.ld.S:
    __INIT_CODE_UNALIGNED__ = .;
    . = ALIGN(PAGE_SIZE);
    __INIT_CODE_END__ = .;
with all the zero data after the last instruction of
BL31 code to the end of the page.
This causes increase in size of BL31 binary stored in FIP
and its loading time by BL2.
This patch reduces the size of BL31 image by moving
page alignment from __INIT_CODE_END__ to __STACKS_END__
which also increases the stack size for secondary CPUs.

Change-Id: Ie2ec503fc774c22c12ec506d74fd3ef2b0b183a9
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

sc7180 platform support ...

Adding support for QTI CHIP SC7180 on ATF

Change-Id: I0d82d3a378036003fbd0bc4784f61464bb76ea82
Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
Co-authored-by: Maulik Shah <mkshah@codeaurora.org>

Merge "MISRA cleanup in mem_region and semihosting files" into integration

lib: cpus: denver: mark exception vectors as private ...

This patch removes the 'workaround_bpflush_runtime_exceptions' exception
vector table base address from the globals list as it gets used only by
the Denver CPU implementation.

Change-Id: I6ef94989f6dc4535d464493cc8621d32795ee1f6
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

MISRA cleanup in mem_region and semihosting files ...

MISRA defect cleanup and general code cleanup in mem_region.c and
semihosting.c.  This task also called for cleanup of the ARM NOR flash
driver but that was removed at some point since the Jira task was
created.  This patch fixes all MISRA defects in these files except for a
few "Calling function "console_flush()" which returns error information
without testing the error information." errors which can't really be
avoided.

Defects Fixed

File                           Line Rule
lib/semihosting/semihosting.c  70   MISRA C-2012 Rule 14.4 (required)
lib/semihosting/semihosting.c  197  MISRA C-2012 Rule 14.3 (required)
lib/semihosting/semihosting.c  210  MISRA C-2012 Rule 14.4 (required)
lib/utils/mem_region.c         128  MISRA C-2012 Rule 12.1 (advisory)

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I21a039d1cfccd6aa4301da09daec15e373305a80

Merge "Fix broken links in docs" into integration

Merge "plat: imx: add sdei support for i.MX8MM" into integration

Fix broken links in docs ...

Change-Id: If82aaba9f2a5a74cfb5e4381f968166037a70037
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

plat: imx: add sdei support for i.MX8MM ...

Add sdei support for i.MX8MM, this is to let jailhouse Hypervisor
could use SDEI to do hypervisor management, after physical IRQ
has been disabled routing.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I5fd697fee22df151e13d0f1335e8ac8a7bae6189

Merge "Initialize platform for MediaTek mt8192" into integration

Merge "BL31: Fix relocation error for PIE" into integration