| 2018-06-21 |
synquacer: Enable System level Generic timer
...
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
|
synquacer: Enable GICv3 support
...
synquacer uses GICv3 compliant GIC500. So enable proper GICv3 driver
initialization.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
|
synquacer: Enable CCN driver support
...
synquacer has CCN-512 interconnect. So enable proper CCN driver
initialization.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
|
synquacer: Implement topology functions
...
These functions describe the layout of the cores and clusters in order
to support the PSCI framework.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
|
synquacer: Populate BL32 and BL33 entrypoints
...
As this platform supports direct entry to BL31 and no BL2, so
populate BL32 and BL33 entrypoints with static memory load info.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
|
synquacer: Enable PL011 UART Console
...
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
|
synquacer: Add platform core management helpers
...
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
|
synquacer: Introduce basic platform support
...
synquacer supports direct entry to BL31 without BL1 and BL2 as
SCP firmware does similar work. So this patch adds BL31 stub APIs.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
|
