2018-12-10 |
io_block: define MAX_IO_BLOCK_DEVICES as unsigned
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This is used as a table index, and already compared with an unsigned int:
block_dev_count.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Yann Gautier
committed
on 10 Dec 2018
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2018-11-08 |
Standardise header guards across codebase
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All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.
The style that this project is now to use the full name of the file in
capital letters followed by 'H'. For example, for a file called
"uart_example.h", the header guard is UART_EXAMPLE_H.
The exceptions are files that are imported from other projects:
- CryptoCell driver
- dt-bindings folders
- zlib headers
Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 8 Nov 2018
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2018-10-30 |
uniphier: revise SCP protocol handshake
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When the SoC issues a command IRQ to SCP, SCP sets STMTOBEIRQ as ACK.
The SoC must wait for it before issuing the next command.
This commit makes sure to meet the requirement.
Signed-off-by: Dai Okamura <okamura.dai@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Dai Okamura
authored
on 4 Oct 2018
Masahiro Yamada
committed
on 30 Oct 2018
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uniphier: terminate boot if SCP_BL2 image is missing in SCP boot mode
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Skipping SCP_BL2 image is just a temporary workaround. If on-chip SCP
needs to work, BL2 should load the SCP_BL2 image.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada
committed
on 30 Oct 2018
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2018-09-28 |
uniphier: Migrate to new interfaces
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- Remove references to removed build options.
- Migrate to bl31_early_platform_setup2().
Change-Id: I9242c4d02a36e385bf0bf8ee56287106030153d1
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 28 Sep 2018
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synquacer: Migrate to new interfaces
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- Remove references to removed build options.
- Update Makefile paths.
- Migrate to bl31_early_platform_setup2().
Change-Id: I51cbf09a0297ac1ee645a959063238c9d556d8e1
Tested-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 28 Sep 2018
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2018-08-30 |
Fix MISRA defects in BL31 common code
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Change-Id: I5993b425445ee794e6d2a792c244c0af53640655
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 30 Aug 2018
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2018-08-22 |
libc: Fix all includes in codebase
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The codebase was using non-standard headers. It is needed to replace
them by the correct ones so that we can use the new libc headers.
Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 22 Aug 2018
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2018-07-25 |
Merge pull request #1486 from antonio-nino-diaz-arm/an/psci-misra
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Fix several MISRA defects in PSCI library
danh-arm
authored
on 25 Jul 2018
GitHub
committed
on 25 Jul 2018
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2018-07-24 |
synquacer: Enable optional OP-TEE support
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OP-TEE loading is optional on Developerbox controlled via SCP
firmware. To check if OP-TEE is loaded or not, we use DRAM1 region
info passed by SCP firmware.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
Sumit Garg
committed
on 24 Jul 2018
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2018-07-20 |
PSCI: Fix types of definitions
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Also change header guards to fix defects of MISRA C-2012 Rule 21.1.
Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 20 Jul 2018
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2018-06-21 |
synquacer: Add platform makefile and documentation
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Add Makefile and plaform definations file.
My thanks to Daniel Thompson and Ard Biesheuvel for the bits and pieces
I've taken from their earlier work regarding build and deploy steps for
Developerbox based on Synquacer SoCs. They deserve much of the credit
for this work although, since I assembled and tested things, any blame
is probably mine.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Tested-by: Daniel Thompson <daniel.thompson@linaro.org>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
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synquacer: Enable PSCI framework
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PSCI framework uses SCPI driver to communicate to SCP firmware for
various power management operations. Following PSCI operations are
supported:
- CPU ON
- CPU OFF
- CPU STANDBY
- SYSTEM RESET
- SYSTEM OFF
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
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synquacer: Retrieve DRAM info from SCP firmware
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Retrieve DRAM info from SCP firmware using SCPI driver. Board supports
multiple DRAM slots so its required to fetch DRAM info from SCP firmware
and pass this info to UEFI via non-secure SRAM.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Ard Biesheuvel
authored
on 15 Jun 2018
Sumit Garg
committed
on 21 Jun 2018
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synquacer: Add SCPI driver
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Add System Control and Power Interface (SCPI) driver which provides APIs
for PSCI framework to work. SCPI driver uses MHU driver APIs to communicate
with SCP firmware for various system control and power operations.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
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synquacer: Add MHU driver
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Add Message Handling Unit (MHU) driver used to communicate among
Application Processors (AP) and System Control Processor (SCP).
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
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synquacer: Enable MMU using xlat_tables_v2 library
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BL31 runs from SRAM which is a non-coherent memory on synquacer. So
enable MMU with SRAM memory marked as Non-Cacheable and mark page tables
kept on SRAM as Non-Cacheable via XLAT_TABLE_NC flag. Also add page tables
for Device address space.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
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synquacer: Enable System level Generic timer
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Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
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synquacer: Enable GICv3 support
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synquacer uses GICv3 compliant GIC500. So enable proper GICv3 driver
initialization.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
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synquacer: Enable CCN driver support
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synquacer has CCN-512 interconnect. So enable proper CCN driver
initialization.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
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synquacer: Implement topology functions
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These functions describe the layout of the cores and clusters in order
to support the PSCI framework.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
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synquacer: Populate BL32 and BL33 entrypoints
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As this platform supports direct entry to BL31 and no BL2, so
populate BL32 and BL33 entrypoints with static memory load info.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
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synquacer: Enable PL011 UART Console
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Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
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synquacer: Add platform core management helpers
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Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
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synquacer: Introduce basic platform support
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synquacer supports direct entry to BL31 without BL1 and BL2 as
SCP firmware does similar work. So this patch adds BL31 stub APIs.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
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2018-06-11 |
uniphier: fix CCI-500 connection for LD20
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The slave ports of LD20 CCI-500 are connected as follows:
S0: CA53
S1: CA72
Be careful because the slave interface is not arranged in the
cluster number order (CA72: cluster 0, CA53: cluster 1).
Root-caused-by: Tetsuya Yoshizaki <yoshizaki.tetsuya@socionext.com>
Signed-off-by: Satoshi Ikawa <ikawa.satoshi@socionext.com>
Satoshi Ikawa
authored
on 11 Jun 2018
Masahiro Yamada
committed
on 11 Jun 2018
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2018-03-26 |
plat: fix switch statements to comply with MISRA rules
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Ensure (where possible) that switch statements in plat comply with MISRA
rules 16.1 - 16.7.
Change-Id: Ie4a7d2fd10f6141c0cfb89317ea28a755391622f
Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>
Jonathan Wright
committed
on 26 Mar 2018
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2018-02-06 |
Merge pull request #1224 from masahir0y/gzip
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Support GZIP-compressed images for faster loading and verification
davidcunado-arm
authored
on 6 Feb 2018
GitHub
committed
on 6 Feb 2018
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2018-02-02 |
uniphier: add ULL to physical address literals
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Looks like this is requirement in the pre-merge static analysis.
misra_violation: [Required] MISRA C-2012 Rule 7.2 violation:
Unsigned constants must be declared with U or u suffix.
Adding ULL as requested. I used ULL() macros for BL*_{BASE,LIMIT}
because they are referenced from linker scripts.
Requested-by: David Cunado <david.cunado@arm.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada
committed
on 2 Feb 2018
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uniphier: allocate xlat region of on-chip SRAM only when needed
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Currently, the xlat region of the on-chip SRAM is always allocated
for all BL images.
The access to the on-chip SRAM is necessary for loading images from
a USB memory device (i.e. when updating firmware), so unneeded for
the usual boot procedure.
To avoid this waste, allocate the xlat region dynamically only for
BL2, and only when it is necessary.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada
committed
on 2 Feb 2018
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