plat: imx8m: Move the gpc hw reg to a separate header file ...

Although the GPC provides the similar functions for all the
i.MX8M SoC family, the HW register offset and bit defines
still have some slight difference, so move the hw reg
offset & most of the bitfield defines in 'gpc_reg.h' that
is specific to each SoC.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I291c435fe98c2f6e6ff8fe0c715ff3a83daa6a0f

arm_fpga: Predefine DTB and BL33 load addresses ...

The memory layout for the FPGA is fairly uniform for most of the FPGA
images, and we already assume that DRAM starts at 2GB by default.

Prepopulate PRELOADED_BL33_BASE and FPGA_PRELOADED_DTB_BASE to some
sane default values, to simplify building some stock image.
If people want to deviate from that, they can always override those
addresses on the make command line.

Change-Id: I2238fafb3f8253a01ad2d88d45827c141d9b29dd
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

arm_fpga: Add Klein and Matterhorn support ...

To support FPGAs with those cores as well, as the respective cpulib
files to the Makefile.

Change-Id: I1a60867d5937be88b32b210c7817be4274554a76
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

arm_fpga: Support more CPU clusters ...

The maximum number of clusters is currently set to 2, which is quite
limiting. As there are FPGA images with 4 clusters, let's increase the
limit to 4.

Change-Id: I9a85ca07ebbd2a018ad9668536d867ad6b75e537
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

stm32mp1: register shared resource per GPIO bank/pin ...

Introduce helper functions stm32mp_register_secure_gpio() and
stm32mp_register_non_secure_gpio() for drivers to register a
GPIO pin as secure or non-secure.

These functions are stubbed when shared resource driver is not
embedded in the BL image so that drivers do not bother whether they
shall register or not their resources.

Change-Id: I1fe98576c072ae31f75427c9ac5c9f6c4f1b6ed1
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

stm32mp1: register shared resource per IOMEM address ...

Introduce helper functions stm32mp_register_secure_periph_iomem()
and stm32mp_register_non_secure_periph_iomem() for drivers to
register a resource as secure or non-secure based on its SoC
interface registers base address.

These functions are stubbed when shared resources driver is not
embedded (!STM32MP_SHARED_RESOURCES) so that drivers embedded
in other BL stages do not bother whether they shall register or
not their resources.

Change-Id: Icebd05a930afc5964bc4677357da5d1b23666066
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

stm32mp1: allow non-secure access to reset upon periph registration ...

Update implementation of stm32mp_nsec_can_access_reset() based
on the registering of the shared resources.

Querying registering state locks further registration of
peripherals.

Change-Id: I5f38f2a3481780b9a71939d95984c4821c537aa4
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

stm32mp1: allow non-secure access to clocks upon periph registration ...

Update implementation of stm32mp_nsec_can_access_clock() based
on the registering of the shared resources.

Querying registering state locks further registration of peripherals.

Change-Id: If68f6d4a52c4742ba66244c6ea2d9afa08404137
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

stm32mp1: shared resources: peripheral registering ...

Define helper functions stm32mp_register_secure_periph() and
stm32mp_register_non_secure_periph() for platform drivers to
register a shared resource assigned to respectively secure
or non-secure world.

Some resources are related to clock resources. When a resource is
registered as secure, ensure its clock dependencies are also
registered as secure. Registering a non-secure resource does not
mandate its clock dependencies are also registered as non-secure.

Change-Id: I74975be8976b8d3bf18dcc807541a072803af6e3
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

stm32mp1: shared resources: add trace messages ...

Define from helper functions to get a human readable string
identifier from a shared resource enumerated ID. Use them to
make debug traces more friendly peripheral registering functions.

Change-Id: I9e207b8ce1d1e9250e242ca7e15461b9a1532f40
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

Merge "Upgrade libfdt source files" into integration

Merge "corstone700: splitting the platform support into FVP and FPGA" into integration

corstone700: splitting the platform support into FVP and FPGA ...

This patch performs the following:

- Creating two corstone700 platforms under corstone700 board:

  fvp and fpga

- Since the FVP and FPGA have IP differences, this commit provides a specific DTS for each platform
- The platform can be specified using the TARGET_PLATFORM Makefile variable
(possible values are: fvp or fpga)
- Allowing to use u-boot by:
  - Enabling NEED_BL33 option
  - Fixing non-secure image base: For no preloaded bl33 we want to
    have the NS base set on shared ram. Setup a memory map region
    for NS in shared map and set the bl33 address in the area.
- Setting the SYS_COUNTER_FREQ_IN_TICKS based on the selected
platform
- Setting ARM_MAP_SHARED_RAM and ARM_MAP_NS_SHARED_RAM to use MT_MEMORY

Change-Id: I4c8ac3387acb1693ab617bcccab00d80e340c163
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>

plat: marvell: armada: a8k: Add support for iEi Puzzle-M801 board ...

Add support for the iEi Puzzle-M801 board that is based on
the Marvell Armada 88F8040 SoC.

It supports 1 x 288-pin DIMM, DDR4 2400MHz up to 16 GB (ECC).

The iEi Puzzle-M801 board is using a custom MCU to handle board
power management. The MCU is managing the boards power LEDs, fans
and some other periferals. It's using UART for communication.

Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Change-Id: I0826ef8bf651b69aad5803184f20930ac7212ef8

plat: marvell: armada: a8k: common: Fix a8k_common.mk to use BOARD_DIR variable ...

Use the BOARD_DIR variable instead of PLAT_FAMILY_BASE variable for
determening the path of the system_power.c file.

The variable was not updated, when it was deprecated in a8k_common.mk
in commit 613bbde.

Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Change-Id: I9b4659a19ba3cd5c869d44c5d834b220f49136e8

Merge "arm_fpga: Fix MPIDR topology checks" into integration

Merge changes from topic "stm32-shres" into integration ...

* changes:
  stm32mp1: shared resources: apply registered configuration
  stm32mp1: shared resources: count GPIOZ bank pins
  stm32mp1: shared resources: define resource identifiers

Merge "stm32mp1: introduce shared resources support" into integration

Merge "plat/arm: Add assert for the valid address of dtb information" into integration

Merge "stm32mp1: disable neon in sp_min" into integration

Merge "stm32mp1: check stronger the secondary CPU entry point" into integration

plat/arm: Add assert for the valid address of dtb information ...

Added assert in the code to check valid address of dtb information
structure retrieved from fw_config device tree.
This patch fixes coverity defect:360213.

Also, removed conditional calling of "fconf_populate" as "fconf_populate"
function already checks the validity of the device tree address received
and go to panic in case of address is NULL.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ib83e4e84a95e2456a12c7a2bb3fe70461d882cba

allwinner: Disable NS access to PRCM power control registers ...

The non-secure world has no business accessing the CPU power switches in
the PRCM; those are handled by TF-A or the SCP. Only allow access to the
clock control part of the PRCM.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I657b97f4ea8a0073448ad3343fbc66ba168ed89e

uniphier: increase BL33 max size and GZIP temporary buffer size ...

The current BL33 size is large enough for U-Boot, but we need to
increase the limit to use other boot loaders such as edk2.

Increase the buffer size used for GZIP decompression too.

 BL33 max size (UNIPHIER_BL33_MAX_SIZE):  1MB -> 8MB
 GZIP buffer (UNIPHIER_IMAGE_BUF_SIZE):   1MB -> 8MB

Increasing the block buffer size (UNIPHIER_BLOCK_BUF_SIZE) is not
required, but I increased it too to make it work more efficiently.

Change-Id: I4fa6d795bed9ab9ada7f8f616c7d47076139e3a8
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Upgrade libfdt source files ...

This version corresponds to the following commit <7be250b>
libfdt: Correct condition for reordering blocks

Also, updated the Juno romlib jumptable with fdt APIs.

Change-Id: Ib6d28c1aea81c2144a263958f0792cc4daea7a1f
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

Merge changes Ib9c82b85,Ib348e097,I4dc315e4,I58a8ce44,Iebc03361, ... into integration ...

* changes:
  plat: marvell: armada: a8k: add OP-TEE OS MMU tables
  drivers: marvell: add support for mapping the entire LLC to SRAM
  plat: marvell: armada: add LLC SRAM CCU setup for AP806/AP807 platforms
  plat: marvell: armada: reduce memory size reserved for FIP image
  plat: marvell: armada: platform definitions cleanup
  plat: marvell: armada: a8k: check CCU window state before loading MSS BL2
  drivers: marvell: add CCU driver API for window state checking
  drivers: marvell: align and extend llc macros
  plat: marvell: a8k: move address config of cp1/2 to BL2
  plat: marvell: armada: re-enable BL32_BASE definition
  plat: marvell: a8k: extend includes to take advantage of the phy_porting_layer
  marvell: comphy: initialize common phy selector for AP mode
  marvell: comphy: update rx_training procedure
  plat: marvell: armada: configure amb for all CPs
  plat: marvell: armada: modify PLAT_FAMILY name for 37xx SoCs

arm_fpga: Fix MPIDR topology checks ...

The plat_core_pos_by_mpidr() implementation for the Arm FPGA port has
some issues, which leads to problems when matching GICv3 redistributors
with cores:
- The power domain tree was not taking multithreading into account, so
  we ended up with the wrong mapping between MPIDRs and core IDs.
- Before even considering an MPIDR, we try to make sure Aff2 is 0.
  Unfortunately this is the cluster ID when the MT bit is set.
- We mask off the MT bit in MPIDR, before basing decisions on it.
- When detecting the MT bit, we are properly calculating the thread ID,
  but don't account for the shift in the core and cluster ID checks.

Those problems lead to early rejections of MPIDRs values, in particular
when called from the GIC code. As a result, CPU_ON for secondary cores
was failing for most of the cores.

Fix this by properly handling the MT bit in plat_core_pos_by_mpidr(),
also pulling in FPGA_MAX_PE_PER_CPU when populating the power domain
tree.

Change-Id: I71b2255fc0d27bfe5806511df479ab38e4e33fc4
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

plat/arm: Use only fw_config between bl2 and bl31 ...

Passed the address of fw_config instead of soc_fw_config
as arg1 to BL31 from BL2 for ARM fvp platform.

BL31 then retrieve load-address of other device trees
from fw_config device tree.

Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ib7e9581cd765d76111dcc3b7e0dafc12503c83c1

Merge changes from topic "fw_config_handoff" into integration ...

* changes:
  doc: Update memory layout for firmware configuration area
  plat/arm: Increase size of firmware configuration area
  plat/arm: Load and populate fw_config and tb_fw_config
  fconf: Handle error from fconf_load_config
  plat/arm: Update the fw_config load call and populate it's information
  fconf: Allow fconf to load additional firmware configuration
  fconf: Clean confused naming between TB_FW and FW_CONFIG
  tbbr/dualroot: Add fw_config image in chain of trust
  cert_tool: Update cert_tool for fw_config image support
  fiptool: Add fw_config in FIP
  plat/arm: Rentroduce tb_fw_config device tree

Merge "stm32mp1: use last page of SYSRAM as SCMI shared memory" into integration