LuminaSensum/arm-trusted-firmware

Fork: 0

LuminaSensum / arm-trusted-firmware

History for arm-trusted-firmware / plat / intel / soc / stratix10

2019-03-13	Unverified c61a807 Browse files » Merge pull request #1874 from hadi-asyrafi/qspi_boot ... intel: QSPI boot enablement Soby Mathew authored on 13 Mar 2019 GitHub committed on 13 Mar 2019
2019-03-12	f5ba408 Browse files » intel: QSPI boot enablement ... Manages QSPI initialization, configuration and IO handling as boot device Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com> Muhammad Hadi Asyrafi Abdul Halim committed on 12 Mar 2019
2019-03-12	150f1bc Browse files » intel: Add driver for QSPI ... To support the enablement of QSPI booting Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com> Muhammad Hadi Asyrafi Abdul Halim committed on 12 Mar 2019
2019-03-08	Unverified 3c652a2 Browse files » Merge pull request #1863 from thloh85-intel/mmc_fixes ... drivers: mmc: Fix some issues with MMC stack Dimitris Papastamos authored on 8 Mar 2019 GitHub committed on 8 Mar 2019
2019-03-07	dd8c03b Browse files » plat: intel: Add MMC OCR voltage information for initialization ... MMC stack needs OCR voltage information for the platform to initialize MMC controller correctly. Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com> Tien Hock, Loh committed on 7 Mar 2019
	Unverified a6561a2 Browse files » Merge pull request #1864 from hadi-asyrafi/mailbox_fix ... intel: Mailbox service un-accessible Dimitris Papastamos authored on 7 Mar 2019 GitHub committed on 7 Mar 2019
	5bd1b44 Browse files » intel: Mailbox service un-accessible ... Change map region for device 2 from non-secure to secure Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com> Muhammad Hadi Asyrafi Abdul Halim committed on 7 Mar 2019
2019-03-06	bf8b8fb Browse files » plat: intel: Improve ECC scrubbing performance ... We should be using zeromem to scrub memory instead of memset. This would improve the performance by 200x Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com> Tien Hock, Loh committed on 6 Mar 2019
2019-02-25	1cf55ab Browse files » plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform ... This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A supports: - PSCI calls to enable 4 CPU cores - PSCI mailbox calls for FPGA reconfiguration Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com> Tien Hock, Loh committed on 25 Feb 2019
2019-02-13	51f366a Browse files » plat: intel: Fix faulty DDR calibration value ... A DDR calibration value is missing write mask, causing ECC DDR calibration to fail. This patch addresses the issue. ECC should also be scrubbed before MMU initializes, thus the scrubbing is moved to ddr intialization phase. Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com> Loh Tien Hock committed on 13 Feb 2019
2019-02-04	9d82ef2 Browse files » plat: intel: Add BL2 support for Stratix 10 SoC ... This adds BL2 support for Intel Stratix 10 SoC FPGA. Functionality includes: - Release and setup peripherals from reset - Calibrate DDR - ECC DDR Scrubbing - Load FIP (bl31 and bl33) Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com> Loh Tien Hock committed on 4 Feb 2019