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2020-10-09	831b0e9 Browse files » Don't return error information from console_flush ... And from crash_console_flush. We ignore the error information return by console_flush in _every_ place where we call it, and casting the return type to void does not work around the MISRA violation that this causes. Instead, we collect the error information from the driver (to avoid changing that API), and don't return it to the caller. Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com> Jimmy Brisson authored on 5 Aug 2020 laurenw-arm committed on 9 Oct 2020
2020-10-04	ff9cfdc Browse files » marvell: comphy: cp110: add support for USB comphy polarity invert ... The polarity inversion for USB was not tested due to lack of hw design which requires it. Currently all supported boards doesn't require USB phy polarity inversion, therefore COMPHY_POLARITY_NO_INVERT is set for all boards. Enable the option for the ones that need it. Change-Id: Ia5f2ee313a93962e94963e2dd8a759ef6d9da369 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Grzegorz Jaszczyk authored on 21 Jan 2020 Marcin Wojtas committed on 4 Oct 2020
	38f6dac Browse files » marvell: comphy: cp110: add support for SATA comphy polarity invert ... The cp110 comphy has ability to invert RX and/or TX polarity. Polarity depends on board design. Currently all supported boards doesn't require SATA phy polarity invert, therefore COMPHY_POLARITY_NO_INVERT is set for all boards. Change-Id: Ifd0bc6aaf8a76a0928132b197422f3193cf020d5 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Grzegorz Jaszczyk authored on 21 Jan 2020 Marcin Wojtas committed on 4 Oct 2020
	8fa1340 Browse files » marvell: comphy: cp110: implement erratum IPCE_COMPHY-1353 ... According to erratum IPCE_COMPHY-1353 the TX_IDLE bit should be toggled in addition to the XFI/SFI PHY reset. Change-Id: Idd2c2abfcb2f960caa01e6d69db524c2e4734f50 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Marcin Wojtas committed on 4 Oct 2020
	11e6ed0 Browse files » drivers: marvell: mochi: Update AP incoming masters secure level ... Do not force non-secure access level for PIDI masters when LLC_SRAM is enabled. The EIP197 is located on CP0 and need to access secure SRAM in AP LLC. This requires EIP197 DMA to have AXPROT[1]=0 and not changed when forwarded to address decoding tables. Change-Id: I8962db94a124350c14220ba6d0364d294ae4664a Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin authored on 22 Aug 2019 Marcin Wojtas committed on 4 Oct 2020
	a9688f0 Browse files » plat: marvell: armada: add ccu window for workaround errata-id 3033912 ... Added ccu window to allow access to addresses in the range [0xf100_0000, 0xf1ff_ffff]. Change-Id: I63ee68338d674114d01cd627198dc907653493e8 Signed-off-by: Alex Leibovich <alexl@marvell.com> Alex Leibovich authored on 25 Dec 2019 Marcin Wojtas committed on 4 Oct 2020
2020-08-11	5e4c97d Browse files » plat: marvell: ap807: implement workaround for errata-id 3033912 ... ERRATA ID: RES-3033912 - Internal Address Space Init state causes a hang upon accesses to [0xf070_0000, 0xf07f_ffff] Workaround: Boot Firmware (ATF) should configure CCU_RGF_WIN(4) to split [0x6e_0000, 0xff_ffff] to values [0x6e_0000, 0x6f_ffff] and [0x80_0000, 0xff_ffff] that cause accesses to the segment of [0xf070_0000, 0xf07f_ffff] to act as RAZWI. Reuse common work-around code for both AP806 and AP807. Change-Id: Ia91a4802d02917d1682faa0c81571093d1687d97 Signed-off-by: Stefan Chulski <stefanc@marvell.com> Stefan Chulski authored on 25 Jun 2019 Marcin Wojtas committed on 11 Aug 2020
2020-07-10	506ff4c Browse files » drivers: marvell: Fix the LLC SRAM driver ... - Fix the line address macro - LLC invalidate and enable before ways lock for allocation - Add support for limited SRAM size allocation - Add SRAM RW test function Change-Id: I1867ece3047566ddd7931bd7472e1f47fb42c8d4 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin authored on 4 Apr 2019 Manish Pandey committed on 10 Jul 2020
	2cae4a8 Browse files » drivers: marvell: mg_conf_cm3: pass comphy lane number to AP FW ... Since the AP process can be enabled on different setups, the information about used comphy lane should be passed to AP FW. For instance: - A8K development board uses comphy lane 2 for eth 0 - cn913x development board uses comphy lane 4 for eth 0 Change-Id: Icf001fb3eea4d9c24c09384e49844ecaf8655ad2 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Grzegorz Jaszczyk authored on 18 Jun 2019 Manish Pandey committed on 10 Jul 2020
	0081cdd Browse files » plat: marvell: armada: move mg conf related code to appropriate driver ... Now when mg_conf_cm3 driver is present - move all relevant code there. Change-Id: I444d9e877c450d6ee69ca3a49b547e4c3aeac0be Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Grzegorz Jaszczyk authored on 17 Apr 2019 Manish Pandey committed on 10 Jul 2020
	5a9e46e Browse files » marvell: comphy: start AP FW when comphy AP mode selected ... After configuring comphy to AP mode also start AP FW. Change-Id: Ib28977d7ee643575a818ba17f69dea0b7e8e0df4 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Grzegorz Jaszczyk authored on 12 Apr 2019 Manish Pandey committed on 10 Jul 2020
	9b88367 Browse files » drivers: marvell: mg_conf_cm3: add basic driver ... Implement function which will allow to start AP FW. Change-Id: Ie0fc8ad138bf56b10809cdc92d1e5e96a2aaf33f Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Grzegorz Jaszczyk authored on 12 Apr 2019 Manish Pandey committed on 10 Jul 2020
2020-06-19	5a40d70 Browse files » drivers: marvell: add support for mapping the entire LLC to SRAM ... Add llc_sram_enable() and llc_sram_disable() APIs to Marvell cache_lls driver. Add LLC_SRAM definition to Marvell common makefile - disabled by the default. Add description of LLC_SRAM flag to the build documentation. Change-Id: Ib348e09752ce1206d29268ef96c9018b781db182 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin authored on 31 Mar 2019 Marcin Wojtas committed on 19 Jun 2020
	957a5ad Browse files » drivers: marvell: add CCU driver API for window state checking ... Add ccu_is_win_enabled() API for checking the CCU window state using AP and window indexes. Change-Id: Ib955a2cac28b2729b0a763f3bbbea28b476a2fe4 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin authored on 31 Mar 2019 Marcin Wojtas committed on 19 Jun 2020
	772aa5b Browse files » drivers: marvell: align and extend llc macros ... Make all LLC-related macros to start with the same prefix Add more LLC control registers definitions This patch is a preparation step for LLC SRAM support Change-Id: I0a4f0fc83e8ef35be93dd239a85f2a9f88d1ab19 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Konstantin Porotchkin authored on 25 Mar 2019 Marcin Wojtas committed on 19 Jun 2020
	050eb19 Browse files » marvell: comphy: initialize common phy selector for AP mode ... Configuring common phy selector which was missing for AP mode. Change-Id: I15be1ba50b8aafe9094734abec139d72c18bb224 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Grzegorz Jaszczyk authored on 28 Mar 2019 Marcin Wojtas committed on 19 Jun 2020
	8e8ec8c Browse files » marvell: comphy: update rx_training procedure ... 1) Relay only on rx training, remove parts responsible for tx training (trx training). 2) Add extra steps e.g. preconfigure FFE before starting training. 3) Remove some unnecessary steps like RRBS31 loopback setting which shouldn't be relevant for tx_training. Change-Id: Ib1e8567714f9ce33578186a262c339aa4b1c51f2 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Grzegorz Jaszczyk authored on 8 Mar 2019 Marcin Wojtas committed on 19 Jun 2020
2020-06-06	615d859 Browse files » ble: ap807: improve PLL configuration sequence ... Update PLL configuration according to HW team guidelines. Change-Id: I23cac4fb4a638e7416965a5399ce6947e08d0711 Signed-off-by: Alex Leibovich <alexl@marvell.com> Alex Leibovich authored on 25 Feb 2019 Marcin Wojtas committed on 6 Jun 2020
	85d2ed1 Browse files » ble: ap807: clean-up PLL configuration sequence ... Remove pll powerdown from pll configuration sequence to improve stability. Remove redundant cases, which no longer exist. Also get rid of irrelevant definition of CPU_2200_DDR_1200_RCLK_1200, which is not used by 806/807. Change-Id: If911e7dee003dfb9a42fafd7ffe34662f026fd23 Signed-off-by: Alex Leibovich <alexl@marvell.com> Alex Leibovich authored on 10 Feb 2019 Marcin Wojtas committed on 6 Jun 2020
	56ad861 Browse files » plat: marvell: mci: perform mci link tuning for all mci interfaces ... This commit introduces two changes: - remove hardcoded references to mci0 from the driver - perform mci optimization for all mci interfaces It fixes performance issues observed on cn9132 CP2. Change-Id: I4e040cd54ff95c9134035ac89b87d8feb28e9eba Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Grzegorz Jaszczyk authored on 6 Feb 2019 Marcin Wojtas committed on 6 Jun 2020
	93574e7 Browse files » plat: marvell: mci: use more meaningful name for mci link tuning ... The mci_initialize function name was misleading. The function itself doesn't initialize MCI in general but performs MCI link tuning for performance improvement. Change-Id: I13094ad2235182a14984035bbe58013ebde84a7e Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Grzegorz Jaszczyk authored on 7 Feb 2019 Marcin Wojtas committed on 6 Jun 2020
	c3c51b3 Browse files » plat: marvell: ap807: update configuration space of each CP ... By default all external CPs start with configuration address space set to 0xf200_0000. To overcome this issue, go in the loop and initialize the CP one by one, using temporary window configuration which allows to access each CP and update its configuration space according to decoding windows scheme defined for each platform. In case of cn9130 after this procedure bellow addresses will be used: CP0 - f2000000 CP1 - f4000000 CP2 - f6000000 When the re-configuration is done there is need to restore previous decoding window configuration(init_io_win). Change-Id: I1a652bfbd0bf7106930a7a4e949094dc9078a981 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Grzegorz Jaszczyk authored on 13 Jan 2019 Marcin Wojtas committed on 6 Jun 2020
	2da75ae Browse files » plat: marvell: ap807: use correct address for MCIx4 register ... The AP807 uses different register offset for MCIx4 register, reflect it in the code. Change-Id: Ic7e44fede3c69083e8629741e7c440b1ae08c35f Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Grzegorz Jaszczyk authored on 13 Jan 2019 Marcin Wojtas committed on 6 Jun 2020
	dc40253 Browse files » plat: marvell: add support for PLL 2.2GHz mode ... Change-Id: Icb8fe14417665d6aadd5a5ee2b77547b4ef78773 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Grzegorz Jaszczyk authored on 20 Dec 2018 Marcin Wojtas committed on 6 Jun 2020
	a284717 Browse files » marvell: armada: add extra level in marvell platform hierarchy ... This commit is a preparation for upcoming support for OcteonTX and OcteonTX2 product families. Armada platform related files (docs, plat, include/plat) are moved to the new "armada" sub-folder. Change-Id: Icf03356187078ad6a2e56c9870992be3ca4c9655 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com> Grzegorz Jaszczyk authored on 5 Nov 2019 Marcin Wojtas committed on 6 Jun 2020
2020-06-03	2d1d2f0 Browse files » marvell: drivers: mochi: specify stream ID for SD/MMC ... This patch enables the stream ID for the SD/MMC controllers via dedicated unit register. Thanks to this change it is possible to configure properly the IOMMU in OS and use the SD/MMC interface in a guest Virtual Machine. Change-Id: I99cbd2c9882eb558ba01405d3d8a3e969f06e082 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Tomasz Nowicki <tn@semihalf.com> Marcin Wojtas committed on 3 Jun 2020
2020-02-25	3968bc0 Browse files » a3700: Use generic console_t data structure ... Since now the generic console_t structure holds the UART base address as well, let's use that generic location and drop the UART driver specific data structure at all. Change-Id: I89c3ab2ed85ab941d8b38ced48474feb4aaa8b7e Signed-off-by: Andre Przywara <andre.przywara@arm.com> Andre Przywara committed on 25 Feb 2020
2020-01-30	8164605 Browse files » plat: marvell: armada: add support for loading MG CM3 images ... In order to access MG SRAM, the amb bridge needs to be configured which is done in bl2 platform init. For MG CM3, the image is only loaded to its SRAM and the CM3 itself is left in reset. It is because the next stage bootloader (e.g. u-boot) will trigger action which will take it out of reset when needed. This can happen e.g. when appropriate device-tree setup (which has enabled 802.3 auto-neg) will be chosen. In other cases the MG CM3 should not be running. Change-Id: I816ea14e3a7174eace068ec44e3cc09998d0337e Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Grzegorz Jaszczyk authored on 18 Aug 2017 Marcin Wojtas committed on 30 Jan 2020
2019-12-11	629dd61 Browse files » drivers: marvell: comphy-a3700: support SGMII COMPHY power off ... Add support for powering off the SGMII COMPHY (on lanes 0 and 1). This is needed sometimes on Turris Mox when using KEXEC. There is also another benefit of a little energy saving when the given network interface is down. Signed-off-by: Marek Behún <marek.behun@nic.cz> Change-Id: I55ae0fe3627e7cc0f65c78a00771939d8bf5399f Marek Behún authored on 5 Nov 2019 Marek Behun committed on 11 Dec 2019
2019-12-11	b662232 Browse files » drivers: marvell: comphy-a3700: fix USB3 powering on when on lane 2 ... When USB3 is on lane 2 and indirect register access is used, the polling at the end of the mvebu_a3700_comphy_usb3_power_on function is incorrect. The LOOPBACK_REG0 register should not be used at all. Instead we have to write the LANE_STATUS1 register address (with offset USB3PHY_LANE2_REG_BASE_OFFSET) into the indirect address register and then we should poll indirect data register. This fixes problems on Turris Mox, which uses lane 2 for USB3. Signed-off-by: Marek Behún <marek.behun@nic.cz> Change-Id: I968b0cccee5ddbe10a2b5614e52e52d87682aacd Marek Behún authored on 8 Oct 2019 Marek Behun committed on 11 Dec 2019