# # Board configuration file for the Zodiac RPU2 board # interface ftdi ftdi_vid_pid 0x0403 0x6011 ftdi_layout_init 0x0038 0x007b ftdi_layout_signal nSRST -data 0x0010 ftdi_layout_signal LED -data 0x0020 transport select jtag reset_config srst_only srst_push_pull connect_deassert_srst # set a slow default JTAG clock, can be overridden later adapter_khz 1000 # need at least 100ms delay after SRST release for JTAG adapter_nsrst_delay 100 # source the target file source [find target/imx7.cfg] source [find mem_helper.tcl] # function to disable the on-chip watchdog proc disable_wdog { } { echo "Bootstrap: Disabling SoC watchdog" mwh phys 0x30280008 0x00 } set ddr_init_failed 0 proc check_bits_set_32 { addr mask } { while { [expr [mrw $addr] & $mask == 0] } { } } proc ddr_init { } { echo "Bootstrap: Initializing DDR" mww phys 0x30340004 0x4F400005 # Clear then set bit30 to ensure exit from DDR retention mww phys 0x30360388 0x40000000 mww phys 0x30360384 0x40000000 mww phys 0x30391000 0x00000002 mww phys 0x307a0000 0x01040001 mww phys 0x307a01a0 0x80400003 mww phys 0x307a01a4 0x00100020 mww phys 0x307a01a8 0x80100004 mww phys 0x307a0064 0x00400046 mww phys 0x307a0490 0x00000001 mww phys 0x307a00d0 0x00020083 mww phys 0x307a00d4 0x00690000 mww phys 0x307a00dc 0x09300004 mww phys 0x307a00e0 0x04080000 mww phys 0x307a00e4 0x00100004 mww phys 0x307a00f4 0x0000033f mww phys 0x307a0100 0x09081109 mww phys 0x307a0104 0x0007020d mww phys 0x307a0108 0x03040407 mww phys 0x307a010c 0x00002006 mww phys 0x307a0110 0x04020205 mww phys 0x307a0114 0x03030202 mww phys 0x307a0120 0x00000803 mww phys 0x307a0180 0x00800020 mww phys 0x307a0184 0x02000100 mww phys 0x307a0190 0x02098204 mww phys 0x307a0194 0x00030303 mww phys 0x307a0200 0x00000016 mww phys 0x307a0204 0x00171717 mww phys 0x307a0214 0x04040404 mww phys 0x307a0218 0x0f040404 mww phys 0x307a0240 0x06000604 mww phys 0x307a0244 0x00000001 mww phys 0x30391000 0x00000000 mww phys 0x30790000 0x17420f40 mww phys 0x30790004 0x10210100 mww phys 0x30790010 0x00060807 mww phys 0x307900b0 0x1010007e mww phys 0x3079009c 0x00000d6e mww phys 0x30790020 0x08080808 mww phys 0x30790030 0x08080808 mww phys 0x30790050 0x01000010 mww phys 0x30790050 0x00000010 mww phys 0x307900c0 0x0e407304 mww phys 0x307900c0 0x0e447304 mww phys 0x307900c0 0x0e447306 check_bits_set_32 0x307900c4 0x1 mww phys 0x307900c0 0x0e447304 mww phys 0x307900c0 0x0e407304 mww phys 0x30384130 0x00000000 mww phys 0x30340020 0x00000178 mww phys 0x30384130 0x00000002 mww phys 0x30790018 0x0000000f check_bits_set_32 0x307900c4 0x1 } # This function applies the initial configuration after a "reset init" # command proc board_init { } { global ddr_init_failed disable_wdog if {[catch {ddr_init} errmsg]} { set ddr_init_failed 1 } else { set ddr_init_failed 0 } } proc safe_reset {} { global ddr_init_failed set status 5 while { $status != 0 } { reset init if { $ddr_init_failed == 1 } { incr status -1 } else { set status 0 } } } proc start_barebox { } { set MX7_DDR_BASE_ADDR 0x80000000 echo "Bootstrap: Loading Barebox" halt load_image images/barebox-zii-imx7d-rpu2.img $MX7_DDR_BASE_ADDR bin arm core_state arm echo [format "Bootstrap: Jumping to 0x%08x" $MX7_DDR_BASE_ADDR] resume $MX7_DDR_BASE_ADDR } # hook the init function into the reset-init event ${_TARGETNAME}.0 configure -event reset-init { board_init }