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barebox / dts / Bindings / arm / altera / socfpga-sdram-edac.txt
@Sascha Hauer Sascha Hauer on 21 Oct 2014 451 bytes dts: update to v3.18-rc1
Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
The EDAC accesses a range of registers in the SDRAM controller.

Required properties:
- compatible : should contain "altr,sdram-edac";
- altr,sdr-syscon : phandle of the sdr module
- interrupts : Should contain the SDRAM ECC IRQ in the
	appropriate format for the IRQ controller.

Example:
	sdramedac {
		compatible = "altr,sdram-edac";
		altr,sdr-syscon = <&sdr>;
		interrupts = <0 39 4>;
	};