barebox/arch/arm/boards/boundarydevices-nitrogen6x/ram-base.imxcfg at 9027f85c62e66bd26a2f65b95e888dce8603773f

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barebox / arch / arm / boards / boundarydevices-nitrogen6x / ram-base.imxcfg

Lucas Stach on 1 Sep 2014 2 KB arm: nitrogen6x: new memory setup from BD u-boot

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wm 32 MX6_IOM_DRAM_SDQS0		0x00000030
wm 32 MX6_IOM_DRAM_SDQS1		0x00000030
wm 32 MX6_IOM_DRAM_SDQS2		0x00000030
wm 32 MX6_IOM_DRAM_SDQS3		0x00000030
wm 32 MX6_IOM_DRAM_SDQS4		0x00000030
wm 32 MX6_IOM_DRAM_SDQS5		0x00000030
wm 32 MX6_IOM_DRAM_SDQS6		0x00000030
wm 32 MX6_IOM_DRAM_SDQS7		0x00000030

wm 32 MX6_IOM_GRP_B0DS			0x00000030
wm 32 MX6_IOM_GRP_B1DS			0x00000030
wm 32 MX6_IOM_GRP_B2DS			0x00000030
wm 32 MX6_IOM_GRP_B3DS			0x00000030
wm 32 MX6_IOM_GRP_B4DS			0x00000030
wm 32 MX6_IOM_GRP_B5DS			0x00000030
wm 32 MX6_IOM_GRP_B6DS			0x00000030
wm 32 MX6_IOM_GRP_B7DS			0x00000030
wm 32 MX6_IOM_GRP_ADDDS			0x00000030
/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
wm 32 MX6_IOM_GRP_CTLDS			0x00000030

wm 32 MX6_IOM_DRAM_DQM0			0x00020030
wm 32 MX6_IOM_DRAM_DQM1			0x00020030
wm 32 MX6_IOM_DRAM_DQM2			0x00020030
wm 32 MX6_IOM_DRAM_DQM3			0x00020030
wm 32 MX6_IOM_DRAM_DQM4			0x00020030
wm 32 MX6_IOM_DRAM_DQM5			0x00020030
wm 32 MX6_IOM_DRAM_DQM6			0x00020030
wm 32 MX6_IOM_DRAM_DQM7			0x00020030

wm 32 MX6_IOM_DRAM_CAS			0x00020030
wm 32 MX6_IOM_DRAM_RAS			0x00020030
wm 32 MX6_IOM_DRAM_SDCLK_0		0x00020030
wm 32 MX6_IOM_DRAM_SDCLK_1		0x00020030

wm 32 MX6_IOM_DRAM_RESET		0x00020030
wm 32 MX6_IOM_DRAM_SDCKE0		0x00003000
wm 32 MX6_IOM_DRAM_SDCKE1		0x00003000

wm 32 MX6_IOM_DRAM_SDODT0		0x00003030
wm 32 MX6_IOM_DRAM_SDODT1		0x00003030

/* (differential input) */
wm 32 MX6_IOM_DDRMODE_CTL		0x00020000
/* (differential input) */
wm 32 MX6_IOM_GRP_DDRMODE		0x00020000
/* disable ddr pullups */
wm 32 MX6_IOM_GRP_DDRPKE		0x00000000
wm 32 MX6_IOM_DRAM_SDBA2		0x00000000
/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
wm 32 MX6_IOM_GRP_DDR_TYPE		0x000C0000

/* Read data DQ Byte0-3 delay */
wm 32 MX6_MMDC_P0_MPRDDQBY0DL	0x33333333
wm 32 MX6_MMDC_P0_MPRDDQBY1DL	0x33333333
wm 32 MX6_MMDC_P0_MPRDDQBY2DL	0x33333333
wm 32 MX6_MMDC_P0_MPRDDQBY3DL	0x33333333
wm 32 MX6_MMDC_P1_MPRDDQBY0DL	0x33333333
wm 32 MX6_MMDC_P1_MPRDDQBY1DL	0x33333333
wm 32 MX6_MMDC_P1_MPRDDQBY2DL	0x33333333
wm 32 MX6_MMDC_P1_MPRDDQBY3DL	0x33333333

/* MDMISC	mirroring	interleaved (row/bank/col) */
wm 32 MX6_MMDC_P0_MDMISC		0x00081740

/* MDSCR	con_req */
wm 32 MX6_MMDC_P0_MDSCR			0x00008000